EP0124402A2
Expired / Lapsed
EP
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Microprocessor
Assignee: Fairchild Semiconductor Corp
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Filing: 1984-03-28
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Granted: —
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Expires: 2004-03-28
Abstract
Abstract A microprocessor data processing system (1700) includes system units (50,1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address. Branch control logic (1938) receives branch conditions inputs and branch control information and generates control signals for a next microaddress multiplexer (1934) in a pipelined instruction path. Microinstructions for the microprocessor (50) are stored for different operations in a microcontrol store (16) with common usage of identical microinstructions for the different operations. A 17th bit auxiliary ALU (1062) in combination with a 16 bith ALU (62) Booth encoder (1074) and overflow logic (1152) implements the modified Booth two shift multiply algorithm. A reduced size constants ROM (120) is provided by generating 28 required constants in the microprocessor with only 5 stored constants through use of a shifter (1066) and a mask (1068). Latches (632) and (634) may be made transparent to reduce execution times in restarts and sequential single microcycle instructions. ALU (62) modifies addresses in instruction counter (200) by subtracting an identifying portion of an aborted microinstruction. Microcode addresses for different types of operations are stored in a mapping PLA (150) by utilizing unused portions of one type of operation address for storing another type of operation address.
Inventors
- 👤 Nabil G. Damouny
- 👤 Min-Siu Huang
- 👤 Yeshayahu Mor
- 👤 Henry C. Lynn
- 👤 Dan Wilnai
- 👤 Michael G. Mladejovsky
- 👤 Yeffi Pilzer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:50
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F13/36; G06F13/362; G06F13/364; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261; G06F9/262; G06F9/264; G06F9/265; G06F9/268; G06F9/30; G06F9/38; G06F9/3861; G06F7/499; G06F7/49905; G06F7/4991
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
118 words
A microprocessor for executing an externally stored program and having a control unit for implementing two levels of pipelining, said control unit comprising: means for receiving instructions and generating address pointers; microcode storage means having microinstructions stored in microaddress locations for receiving said address pointers and for generating microinstruction sequences from those pointers which control the operation of said microprocessor and which, when possible from the external program, fetch the next external program instruction and decode it such that when the present microinstructon sequence is completely executed, the address pointers to the next microinstruction sequence is waiting to address said microcode storage means and the next instruction from the external program has been fetched and is awaiting decoding.
Claim 2
Dependent Claim
118 words
A microprocessor for executing an externally stored program and having a control unit for implementing two levels of pipelining, said control unit comprising: means for receiving instructions and generating address pointers; microcode storage means having microinstructions stored in microaddress locations for receiving said address pointers and for generating microinstruction sequences from those pointers which control the operation of said microprocessor and which, when possible from the external program, fetch the next external program instruction and decode it such that when the present microinstructon sequence is completely executed, the address pointers to the next microinstruction sequence is waiting to address said microcode storage means and the next instruction from the external program has been fetched and is awaiting decoding.
Claim 3
Dependent Claim
129 words
The microprocessor of claim 1 for carrying out arithmetic operations characterized in that each of the operations have a plurality of identical microinstructions common to each operation and at least one different microinstruction for each operation, for causing the microprocessor to carry out the operation, first means for storing the identical microinstructions and the different microinstructions, second means for storing codes identifying each of the operations, means for executing the operations connected to receive-' the microinstructions from said first storing means, and a control means connected between said executing means and said second storing means, said control means being responsive to a code supplied from said second storage means to choose one of the different microinstructions for carrying out the one of the operations corresponding to the supplied code.
Claim 4
Dependent Claim
124 words
The microprocessor of claim 1 characterized by a dynamically reconfigurable pipeline which comprises an instruction register, means for storing microcode addresses connected to receive instructions from said instruction register, a latch connected to receive addresses from said microcode address storage means, said latch being operable in a storage mode and in a transparent mode, means connected to said latch for controlling mode of operation of said latch, a multiplexer connected to receive the addresses from said latch, means for storing the microcode connected to receive the addresses from said multiplexer, and a register for storing a microinstruction to be executed from the microcode, said microinstruction register being connected to receive a microcontrol word from said microcode storing means, said microinstruction register controlling said microprocessor.
Claim 5
Dependent Claim
31 words
The microprocessor of claim 3 characterized in that said means for storing microcode addresses is organized in two sections containing microcode addresses for a derived operand microroutine and an execution microroutine.
Claim 6
Dependent Claim
63 words
The microprocessor of claim 1 characterized by a single programmable logic array containing a plurality of microcode addresses for different types of operations, an instruction register connected to provide inputs to said programmable logic array, a multiplexer connected to provide inputs to said instruction register, said multiplexer receiving the inputs from an information bus and from an output of an operation execution means.
Claim 7
Dependent Claim
247 words
The microprocessor of claim 1 for executing both arithmetic operations in a first plurality of bits and floating point operations in a mantissa field and an exponent field, each having a second plurality of bits lesser than the first plurality of bits, characterized by a microcode storage means storing common microcode instructions utilizable in different floating point operations, a programmable logic array connected to supply addresses to said microcode storage means and to supply a signal indicating floating point operation type to a data path in said microprocessor responsive to the microcode instructions, said data path including means for selectively inhibiting supply of the exponent field when carrying out operations on the mantissa field, means responsive to information in the exponent field for indicating an overflow condition and an underflow condition in the exponent field, means, responsive to said overflow and underflow indicating means, for providing branching instructions during the floating point operations, means for providing an output indicating normalization, said branching instruction providing means also being responsive to the normalization output, means connected to provide a carry in input to the least significant one of the second plurality of bits in the mantissa field in said data path, said data path including a shifter connected to shift and rotate the second plurality of bits in both the mantissa field and the exponent field, a sticky flip-flop connected in said data path, and means connected in said data path to sign extend information in the exponent field.
Claim 8
Dependent Claim
128 words
The microprocessor of claim 1 including a pipelined path for flow of instructions in said microprocessor, characterized by a microcode address multiplexer connected to supply addresses from a plurality of different inputs to a microcode storage means, said microcode storage means being connected to supply microcode in response to the addresses to a microcode register, said microcode register being connected to supply branch control information to a branch control means, said branch control means being connected to receive branch condition inputs externally of said microprocessor, internally of said microprocessor and from a microcode address programmable logic array, said microcode address programmable logic array being connected to supply microcode addresses to said microcode address multiplexer, said branch control means being connected to control operation of said microcode address multiplexer.
Claim 9
Dependent Claim
62 words
The microprocessor of claim 7 characterized in that said microcode programmable logic array is connected to supply microcode addresses to said microcode address multiplexer through a derived operand derived address microroutine address latch and an execution microroutine address latch and the branch condition input to said branch control means identifies which of said latches supplies an address to said microcode address multiplexer.
Claim 10
Dependent Claim
253 words
A microprocessor for carrying out multiplication operations, characterized by means for executing the multiplication operations, a first shifting means connected to receive an output from said multiplication operation executing means, said first shifting means being connected to supply the output to a first register which is connected to supply an input to said multiplication operation execution means, a shift register capable of shifting two places in a single cycle connected to receive the output from said first shifting means, a multiplication control means connected between two least significant bits of said shift register and said multiplication operation execution means, a second shifting means connected between a second register and a first input to said multiplication operation execution means, said second shifting means being controlled by said multiplication control means, an auxiliary multiplication operation execution means connected to receive a most significant bit from said second shifting means and a most significant bit of a secona input to said multiplication operation execution means, a control input from said control means, and a control input from an overflow detecting means, said overflow detecting means being connected to receive a carry input from said multiplication operation execution means and a most significant bit output from said multiplication operation execution means, said auxiliary multiplication operation execution means being connected to supply inputs to two most significant bits of said first shifting means, two most significant bits of said shift register being connected to receive two least significant bits of the output from said multiplication operation execution means.
Claim 11
Dependent Claim
253 words
A microprocessor for carrying out multiplication operations, characterized by means for executing the multiplication operations, a first shifting means connected to receive an output from said multiplication operation executing means, said first shifting means being connected to supply the output to a first register which is connected to supply an input to said multiplication operation execution means, a shift register capable of shifting two places in a single cycle connected to receive the output from said first shifting means, a multiplication control means connected between two least significant bits of said shift register and said multiplication operation execution means, a second shifting means connected between a second register and a first input to said multiplication operation execution means, said second shifting means being controlled by said multiplication control means, an auxiliary multiplication operation execution means connected to receive a most significant bit from said second shifting means and a most significant bit of a secona input to said multiplication operation execution means, a control input from said control means, and a control input from an overflow detecting means, said overflow detecting means being connected to receive a carry input from said multiplication operation execution means and a most significant bit output from said multiplication operation execution means, said auxiliary multiplication operation execution means being connected to supply inputs to two most significant bits of said first shifting means, two most significant bits of said shift register being connected to receive two least significant bits of the output from said multiplication operation execution means.
Claim 12
Dependent Claim
62 words
The microprocessor of claim 9 characterized in that when only said first shifting means shifts, the two most significant bits for said first shifting means are provided by a first exclusive OR gate, said first exclusive OR gate receiving an overflow signal generated by said multiplication operation execution means and the most significant bit of said multiplication operation execution means as inputs.
Claim 13
Dependent Claim
123 words
The microprocessor of claim 9 characterized in that when both said first and second shifting means shift, the penultimate significant bit of said first shifting means is provided by the output of said auxiliary multiplication operation execution means, and the most significant bit of said first shifting means is provided by the output of a first exclusive OR gate, one input of which is the output of said auxiliary multiplication operation execution means, a second input of which is provided by a second exclusive OR gate, one input of which is a carry output signal from a most significant stage of said multiplication operation execution means, a second input of which is a carry output signal of said auxiliary multiplication operation execution means.
Claim 14
Dependent Claim
79 words
A microprocessor for carrying out operations on information using a plurality of constants, characterized by means for executing the operations, means for storing a number of constants less than the plurality of constants, a shifting means connected to receive a constant from said storing means, and a masking means connected to said shifting means, said masking means and said shifting means coacting to produce one of the plurality of constants from one of the constants in said storing means.
Claim 15
Dependent Claim
79 words
A microprocessor for carrying out operations on information using a plurality of constants, characterized by means for executing the operations, means for storing a number of constants less than the plurality of constants, a shifting means connected to receive a constant from said storing means, and a masking means connected to said shifting means, said masking means and said shifting means coacting to produce one of the plurality of constants from one of the constants in said storing means.
Claim 16
Dependent Claim
113 words
A microprocessor for carrying out operations on information based on a pipelined set of variable length instructions, characterized by means for executing the operations, microinstructions for said operation executing means including a portion defining a type of instruction to be fetched, means for terminating execution of the operations under defined conditions, an instruction counter connected to said operation executing means for storing an address of an instruction to be fetched, means responsive to the instruction type identifying portion of the microinstruction for supplying an input to said operation execution means upon termination of instruction execution by said terminating means, for adjusting the address in said instruction counter to that of the terminated instruction.
Claim 17
Dependent Claim
113 words
A microprocessor for carrying out operations on information based on a pipelined set of variable length instructions, characterized by means for executing the operations, microinstructions for said operation executing means including a portion defining a type of instruction to be fetched, means for terminating execution of the operations under defined conditions, an instruction counter connected to said operation executing means for storing an address of an instruction to be fetched, means responsive to the instruction type identifying portion of the microinstruction for supplying an input to said operation execution means upon termination of instruction execution by said terminating means, for adjusting the address in said instruction counter to that of the terminated instruction.
Claim 18
Dependent Claim
28 words
The microprocess of claim 13 characterized in that the address in said instruction counter is adjusted by subtracting the identifying portion from the address in said instruction counter.
Claim 19
Dependent Claim
140 words
A data processing system, comprising a plurality of system units connected in parallel to a common bus, a memory connected to said common bus for access by said system units, and a bus arbiter connected to each of said system units to provide a bus grant signal to a selected one of said system units, each system unit including means for supplying a bus request signal to said bus arbiter, a means responsive to presence of the bus grant signal, a means for supplying a bus lock signal to at least one other of said system units, and a means responsive to absence of the bus lock signal, each of said bus grant signal presence responsive means and said bus lock signal absence responsive means coacting to initiate a bus cycle by their one of said plurality of system units.
Claim 20
Dependent Claim
140 words
A data processing system, comprising a plurality of system units connected in parallel to a common bus, a memory connected to said common bus for access by said system units, and a bus arbiter connected to each of said system units to provide a bus grant signal to a selected one of said system units, each system unit including means for supplying a bus request signal to said bus arbiter, a means responsive to presence of the bus grant signal, a means for supplying a bus lock signal to at least one other of said system units, and a means responsive to absence of the bus lock signal, each of said bus grant signal presence responsive means and said bus lock signal absence responsive means coacting to initiate a bus cycle by their one of said plurality of system units.
Claim 21
Dependent Claim
101 words
A microprocessor characterized by a pending interrupt register connected to mask and enable logic, an output of said mask and enable logic being connected to a priority encoder, said priority encoder being connected to supply a highest priority interrupt value to an interrupt latch in response to an interrupt request supplied to said pending interrupt register, said interrupt latch having a plurality of bits each connected to supply an output to a next adjacent more significant bit of a bus connected to supply the latch outputs to generate a memory address in which a current state of the machine is stored.
Claim 22
Dependent Claim
101 words
A microprocessor characterized by a pending interrupt register connected to mask and enable logic, an output of said mask and enable logic being connected to a priority encoder, said priority encoder being connected to supply a highest priority interrupt value to an interrupt latch in response to an interrupt request supplied to said pending interrupt register, said interrupt latch having a plurality of bits each connected to supply an output to a next adjacent more significant bit of a bus connected to supply the latch outputs to generate a memory address in which a current state of the machine is stored.
References Cited (Backward Citations)
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