EP0122739A2
Expired / Lapsed
EP
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List vector control apparatus
Assignee: Fujitsu Ltd
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Filing: 1984-03-21
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Granted: —
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Expires: 2004-03-21
Abstract
Abstract In a list vector control apparatus to be incorporated in a vector processing system including a plurality of vector registers, one of the vector registers (15-1) is operated as a list vector register loading therein list vector elements, while another vector register (15-2) is operated as a conventional vector register to produce list vector data successively with the aid of its address register (16-2). The address register is connected to a list vector transfer line (61) for transferring the list vector elements sequentially from the list vector register so as to produce the desired list vector data.
Inventors
- 👤 Masanori Mizonokuchi Sukai-Haitsu 114 Motegi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
241 words
A list vector control apparatus incorporated into a vector processor system comprised of, at least, a main memory (11) segmented into N banks (where N is a positive integer equal to or larger than 2) to be accessed under an N-way interleave method, a plurality of vector registers (15-1, 15-2) for loading, from the main memory, successive vector elements therein, a plurality of address registers (16-1, 16-2), allotted to respective vector registers, for accessing the vector elements loaded therein sequentially with each address increment line, and a vector arithmetic unit (19) receiving list vector data sequentially supplied from the vector registers so as to produce resultant data therefrom, characterized in that one of the vector registers (15-1, Figure 6) is operative to load therein a set of list vector elements, as a list vector register, supplied from the main memory; at least one other vector register (15-2, Figure 6) is operative to load therein, from the main memory, a set of vector data elements each corresponding to individual ones of the list vector elements; at least one list vector transfer line (61) is wired between the address register (16-2) of the vector register (15-2) and the list vector register (15-1); and, thereby, the list vector elements are sequentially transferred to and momentarily stored in the address register, via the list vector transfer line, for accessing the vector data elements in the vector register specified thereby, to produce the list vector data.
Claim 2
Dependent Claim
241 words
A list vector control apparatus incorporated into a vector processor system comprised of, at least, a main memory (11) segmented into N banks (where N is a positive integer equal to or larger than 2) to be accessed under an N-way interleave method, a plurality of vector registers (15-1, 15-2) for loading, from the main memory, successive vector elements therein, a plurality of address registers (16-1, 16-2), allotted to respective vector registers, for accessing the vector elements loaded therein sequentially with each address increment line, and a vector arithmetic unit (19) receiving list vector data sequentially supplied from the vector registers so as to produce resultant data therefrom, characterized in that one of the vector registers (15-1, Figure 6) is operative to load therein a set of list vector elements, as a list vector register, supplied from the main memory; at least one other vector register (15-2, Figure 6) is operative to load therein, from the main memory, a set of vector data elements each corresponding to individual ones of the list vector elements; at least one list vector transfer line (61) is wired between the address register (16-2) of the vector register (15-2) and the list vector register (15-1); and, thereby, the list vector elements are sequentially transferred to and momentarily stored in the address register, via the list vector transfer line, for accessing the vector data elements in the vector register specified thereby, to produce the list vector data.
Claim 3
Dependent Claim
75 words
An apparatus as set forth in claim 1, wherein each of the address registers (16-1, 16-2, 16-3, Figure 8) is provided at its input stage with a switcher (62-1, 62-2, 62-3), operative to connect either the said list vector transfer line (61) or the address increment line (63) selectively with the related address register, the switcher selecting the list vector transfer line when list vector processing is to be executed in the vector processing system.
Claim 4
Dependent Claim
32 words
An apparatus as set forth in claim 2, wherein the list vector transfer line (61) is connected between the switcher (62) and the output stage (82) itself of the list vector register.
Claim 5
Dependent Claim
44 words
An apparatus as set forth in claim 2, wherein the list vector transfer line (61) is connected between the switcher (62) and the output of a read vector data register (17-1) connected to the output stage of the list vector register (15-1, Figure 6).
Claim 6
Dependent Claim
122 words
An apparatus as set forth in claim 4, wherein as many OR gates (82) are provided as vector registers, each OR gate being provided, at its input stage, with input gates (83, 84) and being connected at its output stage to an individual address register (16) via the related switcher (62), the input gates (83-3, 84-3) pertaining to one vector register (15-3) being connected to the read vector data registers (17-1, 17-2) pertaining to other vector registers (15-1, 15-2), one of the input gates, pertaining to the vector register for producing the list vector data, being opened to pass the list vector elements, .as addresses, from the read vector data register connected to the vector register operative as the list vector register.
Claim 7
Dependent Claim
169 words
An apparatus as set forth in claim 1, wherein at least three vector registers (91) are provided, one of the vector registers (91-1) being operative as the list vector register, the others of the vector registers (91-2, 91-3) holding the same vector data elements being accessed by the list vector elements from the list vector register to produce therefrom the list vector data, the list vector register being segmented into N to form list vector column registers (91-lL, 91-1R), each of the other vector registers being also segmented into N to form vector column registers (91-2L, 91-2R; 91-3L, 91-3R), each of the vector column registers being operative to load therein the successive vector elements, from the main memory, distributed under an M modulo N process (where M denotes the element number of each vector element), the vector data elements in each vector column register being sequentially accessed by each of the list vector elements loaded in the corresponding list vector column register to produce the list vector data therefrom.
Claim 8
Dependent Claim
139 words
An apparatus as set forth in claim 6, wherein the address registers (16-2L, 16-2R; 16-3L, 16-3R, Figure 10) for individual ones of the N vector column registers (91-2L, 91-2R; 91-3L, 91-3R) are connected, via the list vector transfer line (61-1; 61-2), with a read vector data register (17-1L; 17-1R) for the list vector column regiater (91-1L, 91-1R) corresponding to the N vector column registers to commonly receive upper bits of each of the list vector elements loaded in the read vector data register (17-1L, 17-lR), while the lowermost bit or bits of each of the list vector elements are transferred via a corresponding list vector transfer sub-line (61-l'), the thus transferred lowermost bit or bits being used for selection of one of the list vector data elements accessed by the signal transferred on the list vector transfer line (61).
Claim 9
Dependent Claim
67 words
An apparatus as set forth in claim 7, wherein at least two selection gates (SG10, SG11; SG20, SG21) are provided with individual vector column registers loading therein the vector data elements; a first or a second one of the two selection gates being opened in accordance with the logic "1" or "0" of the lowermost bit when two selection gates are used in an N(=2)-way interleave method.
Claim 10
Dependent Claim
51 words
An apparatus as set forth in claim 8, wherein, when three or more selection gates are used under an N (=3,4 ---)-way interleave method, any one of the three or more selection gates is opened in accordance with the logic values of the lowermost bits with the use of decoder means.
Claim 11
Dependent Claim
69 words
An apparatus as set forth in claim 7, wherein each of the address registers for the vector column registers is provided, at its input stage, with a switcher, operative to connect either the list vector transfer line or the address increment line selectively with the related address register, the switcher selecting the list vector transfer line when list vector processing is to be executed in the vector processing system.
References Cited (Backward Citations)
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