EP0122594A2
Expired / Lapsed
EP
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Line circuit with echo compensation
Assignee: International Standard Electric Corp
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Filing: 1984-04-11
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Granted: —
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Expires: 2004-04-11
Abstract
Abstract A line circuit (1) interposed between two unidirectional digital lines (3,4) and a single bidirectional analog line (2) has a first path (7) in which incoming digital signals are processed and converted into analog signals, and a second path (14) in which outgoing analog signals are converted into digital signals. The two paths (7, 14) are connected to the bidirectional analog line (2) by a common junction (10, 11). A digital hybrid (17) is interposed between the first and second paths (7, 14) and provides compensation for the echo response effects. The digital hybrid (17) is supplied with signals from the first path (7) and with respective correction coefficients. Resultant digital correction signals are combined with the digital signals propagating in the second path (14). To establish the values of the correction coefficients, a training pattern is sent into the line circuit (1), and the responses to the training pattern with the digital hybrid (17) out of operation as obtained at the digital output of the line circuit (1) are then used as the correction coefficients.
Inventors
- 👤 Michael John Gingell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 04:49
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/20; H04B3/23; H04B3/238
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
248 words
A digital communication line circuit (1) interposed between two unidirectional communication lines (3, 4) and a bidirectional communication line (2), including separate first and second communication paths (7, 14) in which first and second signals propagating respectively from one of the unidirectional communication lines (3) toward a junction with the bidirectional communication line (2) and from the junction toward the other unidirectional communication line (4) are respectively constituted by first and second digital signals with a predetermined sample rate, further including digital-to-analog converter means (8) interposed between said first communication path (7) and said junction, and analog-to-digital converter means (13) interposed between said junction and said second communication path (14) and in which echo-compensating means (16) are interposed between the first and second communication paths (7, 14), characterised in that there are means (18) for deriving said first digital signals from said first communication path (7)at a sample rate lower than said predetermined sample rate; and means (17) for generating digital correction signals based on said first digital signals received from said deriving means (18) at said lower sample rate; and means (19, 20) for combining said digital correction signals with said second digital signals in said second communication path (14) such as substantially to eliminate the echoes from said second digital signals, said combining means (19, 20) including means (20) for increasing the sample rate of said digital correction signals to said predetermined sample rate prior to combining said digital correction signals with said second digital signals.
Claim 2
Dependent Claim
248 words
A digital communication line circuit (1) interposed between two unidirectional communication lines (3, 4) and a bidirectional communication line (2), including separate first and second communication paths (7, 14) in which first and second signals propagating respectively from one of the unidirectional communication lines (3) toward a junction with the bidirectional communication line (2) and from the junction toward the other unidirectional communication line (4) are respectively constituted by first and second digital signals with a predetermined sample rate, further including digital-to-analog converter means (8) interposed between said first communication path (7) and said junction, and analog-to-digital converter means (13) interposed between said junction and said second communication path (14) and in which echo-compensating means (16) are interposed between the first and second communication paths (7, 14), characterised in that there are means (18) for deriving said first digital signals from said first communication path (7)at a sample rate lower than said predetermined sample rate; and means (17) for generating digital correction signals based on said first digital signals received from said deriving means (18) at said lower sample rate; and means (19, 20) for combining said digital correction signals with said second digital signals in said second communication path (14) such as substantially to eliminate the echoes from said second digital signals, said combining means (19, 20) including means (20) for increasing the sample rate of said digital correction signals to said predetermined sample rate prior to combining said digital correction signals with said second digital signals.
Claim 3
Dependent Claim
32 words
A line circuit as claimed in claim 1, characterised in that said bidirectional communication line (2) is an analog telephone line, and said unidirectional communisation lines (3, 4) are digital telephone lines.
Claim 4
Dependent Claim
40 words
A line circuit as claimed in claim 1 characterised in that said junction includes an analog hybrid circuit (10) adapted to be interposed between said converters (8, 13) and said bidirectional communication line (2) and including a balance network (11).
Claim 5
Dependent Claim
42 words
A line circuit as claimed in claim 3, characterised in that said balance networt (11) is operative for suppressing analog echoes prior to their transmission from said junction to said analog-to-digital converter (13) at least for certain frequencies of the first signal.
Claim 6
Dependent Claim
102 words
A line circuit as claimed in claim 1, characterised in that a sample rate stepping-up device (5) is arranged ahead of said first communication path (7) as considered in the direction of propagation of said first signals and that a sample rate stepping-down device (5) is arranged behind said second communication path (14) as considered in the direction of propagation of said signals, and that a first filter means (6) is interposed between said stepping-up device (5) and said first communication path (7), and a second filter means (15) is interposed between said second communication path (14) and said stepping-down device (5).
Claim 7
Dependent Claim
78 words
A line circuit as claimed in claim 1 or 5, characterised in that the said first filter means (6) is arranged ahead of said first communication path (7) as considered in the direction of propagation of said first signals, that the said second filter means (15) is arranged behind said second communication path (14) as considered in the direction of propagation of said second signals, and that each of said filter means (6, 15) includes a digital filter.
Claim 8
Dependent Claim
129 words
A line circuit as claimed in claim 1, characterised in that the said echo-compensating means (16) includes a finite impuls response filter (17) which includes a plurality of storage means (21, 22, 23) each for storing one of said first digital signals at said lower sample rate and arranged in series with one another such that the first digital signal previously stored in one of said storage means (21, 22, 23) is transferred at the lower sample rate into the succeeding storage means (22, 23, 21), means (31, 32, 33) for multiplaying the first digital signals available in said filter (17) by respective correction coefficients (a 0 , a 1 , a 2 ), and means (37) for adding the output signals of said multiplying means (31, 32, 33).
Claim 9
Dependent Claim
118 words
A line circuit as claimed in claim 1 or 7, characterised in that said deriving means (18) includes a selector switch (24) interposed between said first communication path (7) and the first of said storage means (21) and operative for supplying the first digital signals to said first storage means (21) at said lower sample rate, and at least one additional selector switch (25, 26) interposed between the respective preceding and succeeding storage means (21, 22, 23) and ganged with said selector switch(24) to transfer the contents of said preceding storage means to said succeeding storage means at said lower sample rate in synchronism with the supply of said first digital signal to said first storage means (21).
Claim 10
Dependent Claim
93 words
A lire circuit as claimes in claim 7, characterised in that said combining means (19, 20) includes a serial adder (19) interposed in said second communication path (14) and having a first input (42) coupled to said adding means (37) and a second input and an output connected to said second communication path (14), and a gate (20') interposed between said adding means {37) and said first input (42) of said serial adder (19) and operated to increase the sample rate of the output of said adding means to said predetermined sample rate.
Claim 11
Dependent Claim
260 words
A line circuit as claimed in claim 5 or 7, characterised in that first signal processing means (5, 6) arranged ahead of said first communication path (7) as considered in the direction of propagation of said first signals, and second signal processing means (15, 5) arranged behind said second communication path (14) as considered in the direction of propagation of said second signals; wherein said correction coefficients (a 0 , a 1 , a 2 ) are capable of being set and said deriving, generating and combining means (17, 18, 19, 20) constitute a unit (16) capable of being rendered inoperative; and further comprising means for determining said correction coefficients (a 0 , a 1 , a 2 ) while said unit (16) is inoperative, in- cluding means (44, 45, 46) for sending a succession of discrete pulses as said first signals into said first communication path (7) through said first signal processing means (5, 6), means (47, 48, 49) for sensing the second signals appearing at the output of said second signal processing means (15, 5) in response to said discrete pulse succession, means for so operating said sending means (44, 45, 46) that said discrete pulse succesion forms a training pattern reflecting the influence of said first and second signal processing means (5, 6 und 15, 5) on said first and second signals, and means (50) for extracting successive outputs of said sensing means (47, 48,49) in response to said training pattern as the values for setting the correction coefficients (a o , a 1' a 2 ).
Claim 12
Dependent Claim
81 words
A line circuit as claimed in claim 10, characterised in that there are means for establishing said training pattern, comprising means for so initially operating said sending means (44, 45, 46) prior to said operating step that said discrete pulses of said succession have equal magnitudes, and means for utilizing the outputs of said sensing means (47, 48, 49) in response to the succession of discrete pulses of equal magnitudes fordetermining the magnitudes of the discrete pulses in said training pattern.
References Cited (Backward Citations)
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