EP0121096A2
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Semiconductor contact structure
Assignee: International Business Machines Corp
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Filing: 1984-02-29
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Granted: —
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Expires: 2004-02-29
Abstract
Abstract A semiconductor contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions (44, 46) of different conductivity type forming a tunnel diode interface therebetween and a conductive segment contiguous to one ofthe two regions. Using such a structure as the source of an FETin a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.
Inventors
- 👤 Paul Evans Bakeman, Jr.
- 👤 Henry John Geipel, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 09:30
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D64/00; H10D64/60; H10D64/62; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A semiconductor structure with at least one FET including a channel region (47) of a first conductivity type interposed between source and drain regions (46, 47) of a second conductivity type formed in a semiconductor layer (42) of a first conductivity type, and a gate electrode (60) adjacent to and insulated from said channel region by a gate dielectric layer (49), characterized in that said source region is a degeneratively doped region (46), that a degeneratively doped contact region (44) of a first conductivity type is contiguously disposed to said source region (46) so as to form a P ++ N ++ junction tunnel diode structure therebetween, and that ohmic contact means (51) are provided on one of said source and contact regions (44, 46) for electrically connecting both source and contact regions to a power source terminal (VDD).
Claim 2
Dependent Claim
139 words
A semiconductor structure with at least one FET including a channel region (47) of a first conductivity type interposed between source and drain regions (46, 47) of a second conductivity type formed in a semiconductor layer (42) of a first conductivity type, and a gate electrode (60) adjacent to and insulated from said channel region by a gate dielectric layer (49), characterized in that said source region is a degeneratively doped region (46), that a degeneratively doped contact region (44) of a first conductivity type is contiguously disposed to said source region (46) so as to form a P ++ N ++ junction tunnel diode structure therebetween, and that ohmic contact means (51) are provided on one of said source and contact regions (44, 46) for electrically connecting both source and contact regions to a power source terminal (VDD).
Claim 3
Dependent Claim
33 words
A semiconductor structure as set forth in claim 1 wherein said semiconductor layer of a first conductivity layer is a well region (42) in a semiconductor body (40) of a second conductivity type.
Claim 4
Dependent Claim
142 words
A semiconductor structure as set forth in claim 1 or 2 further including a second FET complementary to said first FET with said second FET having a channel region (54) of a second conductivity type interposed between source and drain regions (56, 52) of a first conductivity type formed in a predetermined portion of said semiconductor body (40) outside said well region (42), a gate electrode (60) adjacent said semiconductor region and spatially disposed over said channel region and insulated from said semiconductor region by a gate dielectric layer (58); means for interconnecting said first FET and said second FET to form a CMOS circuit arrangement; means for biasing said first FET including said power source terminal, said second FET and said semiconductor body to cause charges to move across said degenerate junction by tunneling and thereby preventing latch-up in the structure.
Claim 5
Dependent Claim
65 words
A semiconductor structure as set forth in claim 3 wherein said source region (56) of said second FET is a degeneratively doped region of a second conductivity type and said semiconductor structure further includes a degeneratively doped contact region (64) of a first conductivity type contiguously disposed to said source region (56) of said second FET so as to form a degenerate PN junction therebetween.
Claim 6
Dependent Claim
148 words
A semiconductor structure of the type having two complementary type FET's monolithically constructed in a semiconductor body (40) of a given conductivity type, with one FET formed in a well region (42) in said semiconductor body (40) having a conductivity opposite to that of said semiconductor body and with each FET having source, channel and drain regions characterized in that at least one of said FET source regions (46, 56) is a degeneratively doped region and contiguously disposed to said degeneratively doped source region is a degeneratively doped contact region (44, 64) having a conductivity type opposite to that of said degeneratively doped source region so that under the proper biasing conditions charges can transfer between said degeneratively doped source and contact regions by tunneling and thereby both degeneratively doped contiguous regions can be brought to substantially the same potential with one connection to a power supply terminal.
Claim 7
Dependent Claim
148 words
A semiconductor structure of the type having two complementary type FET's monolithically constructed in a semiconductor body (40) of a given conductivity type, with one FET formed in a well region (42) in said semiconductor body (40) having a conductivity opposite to that of said semiconductor body and with each FET having source, channel and drain regions characterized in that at least one of said FET source regions (46, 56) is a degeneratively doped region and contiguously disposed to said degeneratively doped source region is a degeneratively doped contact region (44, 64) having a conductivity type opposite to that of said degeneratively doped source region so that under the proper biasing conditions charges can transfer between said degeneratively doped source and contact regions by tunneling and thereby both degeneratively doped contiguous regions can be brought to substantially the same potential with one connection to a power supply terminal.
Claim 8
Dependent Claim
42 words
A semiconductor structure as set forth in claim 5 which is further.characterized in that the size of said degeneratively doped source region and the relative location of said degeneratively doped source and contact regions is preselected to prevent latch-up in said circuit.
Claim 9
Dependent Claim
33 words
A semiconductor structure as set forth in one or more of the preceding claims wherein the degenerate doping concentration in silicon is in excess of 1.8 x 10 19 dopant atoms/cm 3 .
Claim 10
Dependent Claim
51 words
A semiconductor structure as in claim 7 with the doping concentration of the semiconductor body (40) being in the order of 10 15 /cm3 and of the well region (42) being (close to the surface) in the range between 1 x 10 16 to 2 x 10 16 /cm 3 .
Claim 11
Dependent Claim
48 words
A semiconductor structure as set forth in one or more of the preceding claims, particularly according to claim 6, wherein the effective length (X 2 in figs. 56, 52) of the source region (46) is less than the length (X 1 ) of the corresponding contact region (44).
Claim 12
Dependent Claim
41 words
A semiconductor structure as set forth in one or more of the preceding claims wherein the size of the source region (46) relative to the contact region (44) is small thereby minimizing the emitter size of a related parasitic transistor structure.
References Cited (Backward Citations)
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