Memory system

Claim 2

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means (82) for selecting a plurality of memory cells (31) which is arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) which are selected by said first selecting means (82); data being written in or being read out from the memory cells selected by said second selecting means (81), j whereby said memory system being characterized by further comprising third selecting means (83) for selecting a plurality of memory cells (31) which is arranged in said second direction in said memory cell array (32).

Claim 3

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means (82) for selecting a plurality of memory cells (31) which is arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) which are selected by said first selecting means (82), data being written in or being read out from the memory cells (31) selected by said second selecting means (81), whereby said memory system being characterized by further comprising third selecting means (83) for selecting a plurality of memory cells (31) which is arranged in said second direction in said memory cell array (32); and fourth selecting means (84) for selecting at least one memory cell among the memory cells (31) which are selected by said third selecting means (83).

Claim 4

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means (82) for selecting a plurality of memory cells (31) which is arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) which are selected by said first selecting means (82), data being written in or being read out from the memory cells (31) selected by said second selecting means (81), whereby said memory system being characterized by further comprising third selecting means (83) for selecting a plurality of memory cells (31) which is arranged in said second direction in said memory cell array (32); and fourth selecting means (84) for selecting at least one memory cell among the memory cells (31) which are selected by said third selecting means (83).

Claim 5

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means-(82) for selecting in parallel the memory cells (31) of one line which are arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said first selecting means (82), data being written in or being read out from the memory cells selected by said second selecting means (81), whereby said memory system being characterized by further comprising third selecting means (83) for selecting in parallel the memory cells (31) of one line which are arranged in said second direction in said memory cell array (32).

Claim 6

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means-(82) for selecting in parallel the memory cells (31) of one line which are arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said first selecting means (82), data being written in or being read out from the memory cells selected by said second selecting means (81), whereby said memory system being characterized by further comprising third selecting means (83) for selecting in parallel the memory cells (31) of one line which are arranged in said second direction in said memory cell array (32).

Claim 7

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means (82) for selecting in parallel the memory cells (31) of one line which are arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said first selecting means (82), data being written in or being read out from the memory cells (31) selected by said second selecting means (81), whereby said memory system being characterized by further comprsing third selecting means (83) for selecting in parallel the memory cells (31) of one line which are arranged in said second direction in said memory cell array (32), and fourth selecting.means (84) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said third selecting means (83).

Claim 8

A memory system comprising: a memory cell array (32) constituted by a plurality of memory cells (31) which is arranged in a matrix in first and second directions which cross each other; first selecting means (82) for selecting in parallel the memory cells (31) of one line which are arranged in said first direction in said memory cell array (32); and second selecting means (81) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said first selecting means (82), data being written in or being read out from the memory cells (31) selected by said second selecting means (81), whereby said memory system being characterized by further comprsing third selecting means (83) for selecting in parallel the memory cells (31) of one line which are arranged in said second direction in said memory cell array (32), and fourth selecting.means (84) for selecting at least one memory cell among the memory cells (31) of one line which are selected in parallel by said third selecting means (83).

Claim 9

A memory system according to claim 3, charac - terized in that only one of said first selecting means (82) and said third selecting means (83) is made operative in response to a control signal (S).

Claim 10

A memory system according to claim 4, characterized in that only one of said first selecting means (82) and said third selecting means (83) and only one of said second selecting means (81) and said fourth selecting means (84) are respectively made operative in response to said control signal (S).

Claim 11

A memory system according to claim 3, characterized in that said second selecting means (81) selects in parallel two or more memory cells among the memory cells (31) of said one line.

Claim 12

A memory system according to claim 4, characterized in that said fourth selecting means (84) selects in parallel two or more memory celles among the memory cells (31) of said one line.

Claim 13

A memory system according to claim 4, characterized in that each of said second selecting means (81) and said fourth selecting means (84) selects in parallel the same number of memory cells among the memory cells (31) of said respective one line.

Claim 14

A memory system according to claim 3, characterized in that each of said memory cells (31) which constitute said memory cell array (32) consists of: data storing means (43) for storing the data in data storage nodes (48, 49); a first control line (37) to which one selection signal (S.A) to be output from said first selecting means (82) is supplied; a second control line (38) to-which one selection signal (S-C) to be output from said third selecting means (83) is supplied; first and second data transfer lines (33, 34, 35, 36) to which the data is transferred; first switch means (44, 46) inserted among said data storage nodes (48, 49) of said data storing means (43) and said first data transfer lines (33, 34), the conductivity of said first switch means (44, 46) being controlled in response to said signal (S·A) on said first control line (37); and second switch means (45, 47) inserted among said data storage nodes (48, 49) of said data storing means (43) and said second data transfer lines (35, 36), the conductivity of said second switch means (45, 47) being controlled in response to said signal (S·C) on said second control line (38).

Claim 15

A memory system according to claim 4, characterized by further comprising means (71) for reading out the data from each of the memory cells (31) of one line which are selected by said third selecting means (83).

Claim 16

A memory system according to claim 4, characterized by further comprising means (91) for writing the data in and reading the data from the memory cells (31) which are selected by said fourth selecting means (84).

Claim 17

A memory system according to claim 10, characterized by further comprising precharge means (52, 53, 92, 93) for precharging said first and second data transfer lines (33, 34, 35, 36) into a predetermined potential (Vcc).