EP0120303A2
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EP
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Semiconductor memory device having a floating gate electrode
Assignee: Toshiba Corp
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Filing: 1984-02-23
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Granted: —
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Expires: 2004-02-23
Abstract
Abstract A semiconductor memory device having a floating gate transistor and an insulated gate transistor, is provided a p-type semiconductor substrate, first, second and third semiconductor regions which are formed in the surface area of the substrate, a floating gate electrode (65) capacitively coupled through a first insulating layer (61) to a current path including the first and second semiconductor regions (52, 53), a control gate electrode (51) capacitively coupled through a second insulating layer (63) to the floating gate electrode (65), and an insulated gate electrode (71) which is formed through a first insulating layer (69) on that portion of the substrate (50) which lies between the second and third semiconductor regions (53, 54). The first insulating layer (61) of the semiconductor memory device is formed on that portion of the substrate (50) which lies between the first and second semiconductor re g- ions (52, 53). The control gate electrode (51) is a fourth semiconductor region (51) which is formed in the surface area of the substrate (50). A second insulating layer (53) is formed of a very thin monocrystalline oxide layer, and is formed on the fourth semiconductor region (51). The current path of the floating gate transistor is perpendicular to that of the insulated gate transistor substantially in the same plane.
Inventors
- 👤 Junichi Miyamoto
- 👤 Tetsuya Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:55
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B69/00; H10D; H10D30/00; H10D30/60
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
175 words
A semiconductor memory device comprising a semiconductor substrate of one conductivity type (50), first and second semiconductor regions of an opposite conductivity type (52, 53) which are formed in the surface area of said semiconductor substrate (50), a first insulating layer (61) formed on that portion (56) of the semiconductor substrate (50) which lies between said first and second semiconductor regions (52, 53), floating gate electrode (65) which is formed on said first insulating layer (61), a control gate electrode (51), a second insulating layer (63) formed between said control gate electrode (51) and said floating gate electrode (65), and means for applying a voltage between control gate electrode (51) and said second semiconductor region to cause charge carriers to tunnel to and from said floating gate electrode (65) through said first insulating layer (61), characterized in that said control gate (51) is a third semiconductor region of the opposite conductivity type formed in the surface area of said substrate (50), and said second insulating layer (63) is formed on said third semiconductor region (51).
Claim 2
Dependent Claim
175 words
A semiconductor memory device comprising a semiconductor substrate of one conductivity type (50), first and second semiconductor regions of an opposite conductivity type (52, 53) which are formed in the surface area of said semiconductor substrate (50), a first insulating layer (61) formed on that portion (56) of the semiconductor substrate (50) which lies between said first and second semiconductor regions (52, 53), floating gate electrode (65) which is formed on said first insulating layer (61), a control gate electrode (51), a second insulating layer (63) formed between said control gate electrode (51) and said floating gate electrode (65), and means for applying a voltage between control gate electrode (51) and said second semiconductor region to cause charge carriers to tunnel to and from said floating gate electrode (65) through said first insulating layer (61), characterized in that said control gate (51) is a third semiconductor region of the opposite conductivity type formed in the surface area of said substrate (50), and said second insulating layer (63) is formed on said third semiconductor region (51).
Claim 3
Dependent Claim
25 words
A semiconductor memory device according to claim 1, characterized in that said first and second ' insulating layers (61, 63) are formed of monocrystalline layers.
Claim 4
Dependent Claim
29 words
A semiconductor memory device according to claim 2, characterized in that said first insulating layer (61) on said region (53) has a thickness of not more than 100 A.
Claim 5
Dependent Claim
28 words
4 . A semiconductor memory device according to claim 2, characterized in that said second insulating layer (63) has a thickness of not more than 10 0 A.
Claim 6
Dependent Claim
32 words
A semiconductor memory device according to claim 2, characterized in that said second insulating layer (63) has a thickness which is substantially equal to a thickness of said first insulating layer (61).
Claim 7
Dependent Claim
50 words
A semiconductor memory device according to claim 1, characterized in that said first and second semiconductor regions (52, 53) and that portion (56) of said semiconductor substrate which lies between said first and second semiconductor regions constitute a current path of a floating gate transistor which extends in one direction.
Claim 8
Dependent Claim
30 words
A semiconductor memory device according to claim 6, characterized in that said third semiconductor region (51).extends substantially parallel to the current path (52, 56, 53) of said floating gate transistor.
Claim 9
Dependent Claim
99 words
A semiconductor memory device according to claim 6, characterized by further comprising fourth and fifth semiconductor regions (53, 54) of the opposite conductivity type which are formed in the surface area of said semiconductor substrate (50), a third insulating layer (69) formed on that portion (57) of said semiconductor substrate (50) which lies between said fourth and fifth semiconductor regions (53, 55), and a insulated gate electrode (71) formed on said third insulating layer (69); said fourth and fifth semiconductor regions (53, 54), said third insulating layer (69) and a insulated gate electrode (71) constituting an insulated gate transistor.
Claim 10
Dependent Claim
77 words
A semiconductor memory device according to claim 8, characterized in that said fourth and fifth semiconductor regions (53, 54) and that portion of said semiconductor substrate (50) which lies between said fourth and fifth semiconductor regions (53, 54) constitute a current path (52, 56, 53) of said insulated gate transistor which extends substantially perpendicular to the current path of said floating gate transistor, said fourth semiconductor region (53) being electrically coupled to said second semiconductor region (53).
Claim 11
Dependent Claim
36 words
A semiconductor memory device according to claim 9, characterized in that said insulated gate electrode (71) of said insulated gate transistor extends substantially parallel to the current path (52, 56, 53) of said floating gate transistor.
Claim 12
Dependent Claim
40 words
A semiconductor memory device according to claim 9, characterized in that said fifth semiconductor region (54) is connected to a first conductive line (73) which is substantially perpendicular to the current path (52, 56, 53) of said floating gate transistor.
Claim 13
Dependent Claim
40 words
A semiconductor memory device according to claim 9, characterized in that said first semiconductor region (52) is connected to a second conductive line (77) which extends substantially perpendicular to the current path (52, 56, 53) of said floating gate transistor.
Claim 14
Dependent Claim
27 words
A semiconductor memory device according to claim 8, characterized in that said floating gate electrode (65) and said insulated gate electrode (71) are formed of polycrystalline layers.
Claim 15
Dependent Claim
41 words
A semiconductor memory device according to claim 8, characterized in that said first to fifth semiconductor regions (51, 52, 53, 54) are isolated from each other by oxide layers (59) which are inserted at least partially in said semiconductor substrate (50):
Claim 16
Dependent Claim
48 words
A semiconductor memory device according to claim 1, characterized by further comprising a third insulating layer covering said floating gate electrode (65), a conductive layer (86) formed on said third insulating layer, and means (90, 92) for connecting said third semiconductor region (51) to said conductive layer (86).
References Cited (Backward Citations)
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