EP0118921A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
MOSFET with high density of integration and low on resistance
Assignee: Nissan Motor Co Ltd
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Filing: 1984-03-13
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Granted: —
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Expires: 2004-03-13
Abstract
Abstract A vertical type MOSFET having a high degree of integration and a low ON resistance is shown. This device is formed so that the drain region has low resistivity part between well regions and the high resistivity part with which the bottoms of the well regions are in contact. Thereby provided is the MOSFET which has low ON resistance and a high breakdown voltage in spite of its high degree integration.
Inventors
- 👤 Wataru Akiyama
- 👤 Teruyoshi Mihara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 03:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D30/662
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
155 words
A MOSFET with a high density of integration and a low ON resistance comprising: a semiconductor substrate of a first conductivity type; a first drain region of said first conductivity type formed on top of said semiconductor substrate; a second drain region of said first conductivity type formed on top of said first drain region; said second drain region has a lower resistivity than said first drain region; well regions of the second conductivity type opposite to said first conductivity type; said well region being adjacent to said second drain region and in contact with said first drain region at the bottom portions thereof; source regions inside said well regions; a drain electrode formed on the bottom surface of said semiconductor substrate; gate electrodes formed through electrically insulating films on top of channels which are formed by the said well regions; and at least one source electrode being in electrical contact with said source regions.
Claim 2
Dependent Claim
155 words
A MOSFET with a high density of integration and a low ON resistance comprising: a semiconductor substrate of a first conductivity type; a first drain region of said first conductivity type formed on top of said semiconductor substrate; a second drain region of said first conductivity type formed on top of said first drain region; said second drain region has a lower resistivity than said first drain region; well regions of the second conductivity type opposite to said first conductivity type; said well region being adjacent to said second drain region and in contact with said first drain region at the bottom portions thereof; source regions inside said well regions; a drain electrode formed on the bottom surface of said semiconductor substrate; gate electrodes formed through electrically insulating films on top of channels which are formed by the said well regions; and at least one source electrode being in electrical contact with said source regions.
Claim 3
Dependent Claim
21 words
A MOSFET of claim 1, wherein said gate electrode spans said second drain region between adjacent ones of said well regions.
Claim 4
Dependent Claim
20 words
A MOSFET of claim 2, wherein said semiconductor substrate having a higher conductivity than that of said first drain region.
Claim 5
Dependent Claim
21 words
A MOSFET of claim 3, wherein the distance between adjacent ones of said well regions is at least less than 5µm.
Claim 6
Dependent Claim
35 words
A MOSFET of claim 3, further comprising well contact regions of said second conductivity type provided in the centers of said well regions and being in contact with said well regions and said source electrodes.
Claim 7
Dependent Claim
38 words
A MOSFET of claim 1, further comprising low resistivity buried regions of said first conductivity type which is located at the boundary between said substrate and said first drain region and between adjacent ones of said well region.
References Cited (Backward Citations)
No citation records indexed.
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