Instruction fetch apparatus and method of operating same

Claim 2

An instruction fetch apparatus for a data processing system characterized by a look-aside buffer means for storing instructions prior to their execution; control means coupled to said look-aside buffer means for providing a loop mode of operation of said look-aside buffer means; said control means further comprising: comparing means for comparing a new instruction address with a previous instruction address; said comparing means providing a first control signal when said new instruction address and said p re- vious instruction address are equal and latch means coupled to said comparing means for enabling the extraction of instructions from said look-aside buffer means upon the presence of said first control signal; whereby fetch operations from storage are reduced due to the ability to extract instructions to be executed directly from said look-aside buffer means when said instruction fetch apparatus is in loop mode.

Claim 3

An instruction fetch apparatus for a data processing system comprising a storage means, an instruction counter means, characterized by a look-aside buffer means coupled to said instruction counter means for storing a predetermined maximum number of instructions prior to their re-execution; an instruction buffer means coupled to said storage means for storing instructions fetched from said storage means; an instruction register means coupled to said instruction buffer means and said look-aside buffer means for facilitating the decoding and execution of instructions received from said instruction buffer means when said instruction fetch apparatus is in normal mode and from said look-aside buffer means when said instruction fetch apparatus is in loop mode; control means coupled to said instruction counter means and said look-aside buffer means for placing said instruction fetch apparatus in either normal mode or loop mode; said control means further comprising: a new target address register means for storing the target address of a new branch instruction; an old target address register means for storing the target address of an old branch instruction; a first comparing means coupled to said new target address register means and said old target address register means for providing a first control signal when the target address of said new branch instruction is equal to the target address of said old branch instruction; a source address register means for storing the source address associated with said new branch instruction; a subtracting and zero detect means coupled to said old target address register means and said source address register means for providing a second control signal when the difference between the target address of said old branch instruction and the source address associated with said new branch instruction is within a predetermined range; a logic means coupled to said first comparing means and said subtracting and zero detect means for placing said instruction fetch apparatus in loop mode when both said first control signal and said second control signal are present and a second comparing means coupled to said source address register means for placing said instruction fetch apparatus in normal mode when the current instruction address is greater than or equal to the source address associated with said new branch'instruction; whereby instructions are fetched from said storage means when said instruction fetch apparatus is in normal mode and directly from said look-aside buffer means when said instruction fetch apparatus is in loop mode.

Claim 4

An instruction fetch apparatus for a data processing system comprising a storage means, an instruction counter means, characterized by a look-aside buffer means coupled to said instruction counter means for storing a predetermined maximum number of instructions prior to their re-execution; an instruction buffer means coupled to said storage means for storing instructions fetched from said storage means; an instruction register means coupled to said instruction buffer means and said look-aside buffer means for facilitating the decoding and execution of instructions received from said instruction buffer means when said instruction fetch apparatus is in normal mode and from said look-aside buffer means when said instruction fetch apparatus is in loop mode; control means coupled to said instruction counter means and said look-aside buffer means for placing said instruction fetch apparatus in either normal mode or loop mode; said control means further comprising: a new target address register means for storing the target address of a new branch instruction; an old target address register means for storing the target address of an old branch instruction; a first comparing means coupled to said new target address register means and said old target address register means for providing a first control signal when the target address of said new branch instruction is equal to the target address of said old branch instruction; a source address register means for storing the source address associated with said new branch instruction; a subtracting and zero detect means coupled to said old target address register means and said source address register means for providing a second control signal when the difference between the target address of said old branch instruction and the source address associated with said new branch instruction is within a predetermined range; a logic means coupled to said first comparing means and said subtracting and zero detect means for placing said instruction fetch apparatus in loop mode when both said first control signal and said second control signal are present and a second comparing means coupled to said source address register means for placing said instruction fetch apparatus in normal mode when the current instruction address is greater than or equal to the source address associated with said new branch'instruction; whereby instructions are fetched from said storage means when said instruction fetch apparatus is in normal mode and directly from said look-aside buffer means when said instruction fetch apparatus is in loop mode.

Claim 5

An instruction fetch apparatus according to claim 1 or 2 characterized in that said look-aside buffer means further includes: an instruction array means for storing a predetermined maximum number of instructions that are latched into said instruction register means from said instruction buffer means during normal mode; an associativity array means for storing address bits corresponding to the instructions stored in said instruction array means; a valid bit flag means coupled to said associativity array means for verifying the validity of each address stored in said associativity array; an incrementing pointer means coupled to said valid bit flag means and said instruction array means for selecting a next sequential entry in said instruction array means and said associativity array means; a third comparing means coupled to said associa - tivity array means for comparing the contents of said instruction counter means with the addresses stored in said associativity array means and a hit logic means coupled to said third comparing means and said instruction array means for latching an instruction stored in said instruction array means into said instruction register means during loop mode.

Claim 8

A method according to claim 4 characterized by additionally including the steps of comparing the source address associated with said new branch instruction with the address of the current instruction and placing said data processing system in normal mode when the address of said current instruction is greater than or equal to the source address associated with said new branch instruction.

Claim 11

A method according to claim 6 characterized by additionally including the steps of comparing the source address associated with said new branch instruction with the address of the current instruction and resuming the fetching of instructions to be executed from said storage means and terminating the latching of instructions from said instruction array means directly into said instruction register means when the address of said current instruction is greater than or equal to the source address associated with said new branch instruction.

Claim 12

A method according to claim 6 or 7 characterized by additionally comprising the step of resuming the fetching of instructions to be executed from said storage means and terminating the latching of instructions from said instruction array means directly into said instruction register means when no match occurs between address bits of the current instruction and address bits stored in said associativity array means.

Claim 13

A method according to claim 7 characterized by further including the step of invalidating at least one of the addresses stored in said associativity array means when the address of said current instruction is greater than the source address associated with said new branch instruction.

Claim 14

A method according to claim 7 or 8 characterized by further including the step of invalidating the entire set of addresses stored in said associativity array means when an operation result is stored in said storage means within a range of said current instruction defined by the predetermined maximum number of instructions stored in said instruction array means.

Claim 15

A method according to claim 7 or 8 characterized by further including the step of invalidating the entire set of addresses stored in said associativity array means when virtual to real address mapping is changed.

Claim 16

A method according to claim 8 characterized by further including the step of invalidating at least one of the addresses stored in said associativity array means when no match occurs between the address of the current instruction and an address stored in said associativity array means.

Claim 17

A method according to claim 9 characterized by further including the step of invalidating the entire set of addresses stored in said associativity array means when an operation result is stored in said storage means within a range of said current instruction defined by the predetermined maximum number of instructions stored in said instruction array means.

Claim 18

A method according to claim 9 characterized by further including the step of invalidating the entire set of addresses stored in said associativity array means when virtual to real address mapping is changed.

Claim 19

A method according to claim 11 characterized by further including the step of invalidiating the entire set of addresses stored in said associativity array means when virtual to real address mapping is changed.

Claim 20

An instruction fetch apparatus for a data processing system characterized by a storage means and an instruction counter means; a look-aside buffer means coupled to said instruction counter means for storing a predetermined number of instructions prior to their execution; said look-aside buffer means further including a first comparing means for placing said instruction fetch apparatus in normal mode when the current instruction address in said instruction counter is not stored in said look-aside buffer means; an instruction buffer means coupled to said storage means for storing instructions fetched from said storage means; an instruction register means coupled to said instruction buffer means and said look-aside buffer means for facilitating the decoding and execution of instructions received from said instruction buffer means when said instruction fetch apparatus is in normal mode and from said look-aside buffer means when said instruction fetch apparatus is in loop mode; control means coupled to said instruction counter means and said look-aside buffer means for placing said instruction fetch apparatus in loop mode; said control means further comprising: a new target address register means for storing the target address of a new branch instruction; an old target address register means for storing the target address of an old branch instruction; a second comparing means coupled to said new target address register means and said old target address register means for providing a first control signal when the target address of said new branch instruction is equal to the target address of said old branch instruction; a source address register means for storing the source address associated with said new branch instruction; a subtracting and zero detect means coupled to said old target address register means and said source address register means for providing a second control signal when the difference between the target address of said old branch instruction and the source address associated with said new branch instruction is within a predetermined range; and a logic means coupled to said first comparing means and said subtracting and zero detect means for placing said instruction fetch apparatus in loop mode when both said first control signal and said second control signal are present whereby instructions are fetched from said storage means when said instruction fetch apparatus is in normal mode and directly from said look-aside buffer means when said instruction fetch apparatus is in loop mode.

Claim 21

An instruction fetch apparatus for a data processing system characterized by a storage means and an instruction counter means; a look-aside buffer means coupled to said instruction counter means for storing a predetermined number of instructions prior to their execution; said look-aside buffer means further including a first comparing means for placing said instruction fetch apparatus in normal mode when the current instruction address in said instruction counter is not stored in said look-aside buffer means; an instruction buffer means coupled to said storage means for storing instructions fetched from said storage means; an instruction register means coupled to said instruction buffer means and said look-aside buffer means for facilitating the decoding and execution of instructions received from said instruction buffer means when said instruction fetch apparatus is in normal mode and from said look-aside buffer means when said instruction fetch apparatus is in loop mode; control means coupled to said instruction counter means and said look-aside buffer means for placing said instruction fetch apparatus in loop mode; said control means further comprising: a new target address register means for storing the target address of a new branch instruction; an old target address register means for storing the target address of an old branch instruction; a second comparing means coupled to said new target address register means and said old target address register means for providing a first control signal when the target address of said new branch instruction is equal to the target address of said old branch instruction; a source address register means for storing the source address associated with said new branch instruction; a subtracting and zero detect means coupled to said old target address register means and said source address register means for providing a second control signal when the difference between the target address of said old branch instruction and the source address associated with said new branch instruction is within a predetermined range; and a logic means coupled to said first comparing means and said subtracting and zero detect means for placing said instruction fetch apparatus in loop mode when both said first control signal and said second control signal are present whereby instructions are fetched from said storage means when said instruction fetch apparatus is in normal mode and directly from said look-aside buffer means when said instruction fetch apparatus is in loop mode.

Claim 22

An instruction fetch apparatus according to claim 16 characterized in that said look-aside buffer means further includes: an instruction array means for storing a predetermined maximum number of instructions that are latched into said instruction register means from said instruction buffer means during normal mode; an associativity array means coupled to said first comparing means for storing address bits corresponding to the instructions stored in said instruction array means; a valid bit flag means coupled to said associativity array means for verifying the validity of each address entry stored in said associativity array; an incrementing pointer means coupled to said valid bit flag means and said instruction array means for selecting a next sequential entry in said instruction array means and said associativity array means; a hit logic means coupled to said first comparing mens and said instruction array means for latching an instruction stored in said instruction array means into said instruction register means during loop mode.

Claim 23

An instruction fetch apparatus according to claim 16 characterized in that said control means further includes a third comparing means coupled to said source address register means for placing said instruction fetch apparatus in normal mode when the current instruction address is greater than or equal to the source address associated with said new branch instruction.