Distributed-structure circuit for arbitrating the access requests to the bus of a multiprocessor system

Claim 1

Circuit for arbitrating the access requests to a bus (B) by elements (MP1, MP2, ...) of a multiprocessor system, said circuit having a distributed structure composed of equal arbitrating devices (ARB1, ARB2, ...), each connected to the corresponding element and interconnected via a priority bus (P) having a binary-tree structure, and for the initialization procedures connected in series, the available time for accessing the bus being subdivided into successive cycles, characterized in that each of said arbitrating devices (ARBl) comprises: - a comparator (COMP) which receives at the inputs said priority bus (P), on which there is present a binary-number forming a priority vector p, and a first internal bus (R) carrying a binary number forming a present priority vector r, and which emits an equality signal (EQ) of data present on said input buses; - a computing circuit (NP) of the future priority which receives at the inputs said priority bus (P) and first internal bus (R) and emits on a second internal bus (D) a binary number, which forms a future priority vector d, computed starting from the most significant position according to the following Boolean equations: where equation (1) is valid for the bits of the moat significant position of the vectors, the equation (2) is valid for the bits of all the other positions, symbols d (j), p (j), r (j) indicate the bit having j -th weight of the respective vectors d, p, r, while the symbols XOR and * indicate EX-OR and AND logic operations; - a first transmission circuit (DR1) for sending on a fourth internal bus (Dl) said future priority vector d present on said second internal bus (D) only when it receives a first enabling signal (AB1); - a decrement logic (LD) subtracting a fixed binary number from said priority vector p present on the priority bus (P) and obtaining and sending on a third internal bus (U) an initial-priority vector i; - a second transmission circuit (DR2) sending on said fourth internal bus (Dl) said initial-priority vector i present on said third internal bus (U) only when it receives a second enabling signal (AB2); - an internal register (RGI) memorizing and supplying on said first internal bus (R) the priority vector present on said fourth internal bus (Dl); - a third transmission circuit (DR3), sending on said priority bus (P) the priority vector present on said first internal bus (R), only when it receives a third enabling signal (AB3); - a control logic (UCl) carrying out in sequence the following operations: when it receives a reset signal (RS), it emits an inhibition signal (LK) of the arbitrating procedures of all the arbitrating devices for the subsequent cycles, and, if an initialization signal (IN1) emitted by the upstream arbitrating device is active, it emits said second (AB2) and then said third (AB3) enabling signal and then an initialization signal (IH2), towards the downstream arbitrating device; when said inhibition signal (LK) is deactivated it emits said first enabling signal (ABl), and, if a signal of access request to the bus (B) coming from the respective element (MP1) is present, it emits said third enabling signal (AB3); if it receives said equality signal (EQ) from said comparator (COMP) it emits towards the respective element (MP 1) a signal (AK1) indicating the occurred bus acquisition; then if the element (MP1) has sent a signal (CN1) of request of the bus (B) for a plurality of cycles, it emits said inhibition signal (LK) up to the last but one cycle requested, else it emits said first enabling signal (AB1).