Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
265 words
Priority system for use in the channel subsystem of a data processing system providing a selectable relative priority between secondary data stagers and an I/O processor for access to the system resources, including logic circuits and lines for granting an operating cycle to a requester on the basis of one of a plurality of priority sequences among the requesters, stepping means for stepping the circuit means through the cycle of priority sequences, and means for changing the stepping sequence, characterized by means for signaling the availability of the resources (33-37), means for signaling a request for one or more of said resources by a requester (30-32), and means (48-53) for matching the requests and the availability signals and signaling a generalized request (line 39) by the requester if a match is found, by means responsive to a generalized request (39, 62, 63) for granting access (64-66) to a requester on the basis of a selected one of all combinations of the priority sequences, means (72 and 73) for controlling said granting means to operate according to a particular priority sequence and for stepping said granting means through said combinations in a predetermined sequence in which one requester (IOP on line 63) has highest priority only once and another requester (SDSl on line 39 or SDS2 on line 62) has highest priority several times, and by means (69) for signaling said controlling means (72 and 73) to omit selected ones of the steps in which said one requester has highest priority, whereby the relative priority of the requesters over a cycle of steps is made variable.
Claim 2
Dependent Claim
265 words
Priority system for use in the channel subsystem of a data processing system providing a selectable relative priority between secondary data stagers and an I/O processor for access to the system resources, including logic circuits and lines for granting an operating cycle to a requester on the basis of one of a plurality of priority sequences among the requesters, stepping means for stepping the circuit means through the cycle of priority sequences, and means for changing the stepping sequence, characterized by means for signaling the availability of the resources (33-37), means for signaling a request for one or more of said resources by a requester (30-32), and means (48-53) for matching the requests and the availability signals and signaling a generalized request (line 39) by the requester if a match is found, by means responsive to a generalized request (39, 62, 63) for granting access (64-66) to a requester on the basis of a selected one of all combinations of the priority sequences, means (72 and 73) for controlling said granting means to operate according to a particular priority sequence and for stepping said granting means through said combinations in a predetermined sequence in which one requester (IOP on line 63) has highest priority only once and another requester (SDSl on line 39 or SDS2 on line 62) has highest priority several times, and by means (69) for signaling said controlling means (72 and 73) to omit selected ones of the steps in which said one requester has highest priority, whereby the relative priority of the requesters over a cycle of steps is made variable.
Claim 3
Dependent Claim
255 words
A priority system for a data processing system according to claim 1, characterized by circuit means for each requester (30-32) for matching requests for access to one or more resources (33-37) with the availability of resources, and means for signaling a general request for the associated requester when a match has been found, by means responsive to the general request signals from each of the requesters (30-32) for granting access to one requester, by a plurality of signal lines (39, 62, 63, 69) and means (Fig. 2) for producing a signal on the lines one at a step in a first predetermined sequence in which each line carries a signal for one step of resource allocation in a repeating cycle of steps, each line corresponding to a particular sequence of priority among the requesters, by said first sequence being longer than the number of combinations of the requesters whereby certain sequences of priority appear more than once in a cycle and different requesters have different priority to resource access during a cycle, by logic means responsive to said signal lines and to said general requests to grant access to one of the requesters in a priority sequence that is established by the particular line carrying a signal for a step, and by means for controlling said means for producing a signal on said lines to operate in a second predetermined sequence in which there are fewer steps than in said first sequence and the relative priority of the requesters during a complete cycle is changed.
Claim 4
Dependent Claim
41 words
The priority system of Claim 2 wherein said means for producing a signal on said lines includes means for producing a signal on a line to grant access to the lowest priority requester on at least one step in each cycle.
Claim 5
Dependent Claim
25 words
The priority system of Claim 3 wherein said means for producing a signal comprises a sequential circuit having a state for each of said lines.
Claim 6
Dependent Claim
23 words
The priority system of Claim 4 wherein said means for controlling includes means for changing the sequence of states in said sequential circuit.
Claim 7
Dependent Claim
23 words
The priority system of Claim 5 wherein said means for controlling includes means for receiving a multi-bit code defining the sequence of states.