EP0118158A2
Expired / Lapsed
EP
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Programmable read-only memory structure and method of fabricating such structure
Assignee: Koninklijke Philips NV
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Filing: 1984-03-05
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Granted: —
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Expires: 2004-03-05
Abstract
Abstract A programmable read only memory structure is formed in oxide isolated regions of a crystalline semiconductor body. The memory elements in an isolated region include a semiconductive junction diode formed by implanting or diffusing a first surface region of opposite conductivity type in the body of first conducitivity type. The programmable element of the diode array comprises a second region formed as a surface layer in the first surface region. The second region is formed by implanting ions of sufficient energy and density to convert the surface layer of the first region from crystalline to amorphous form. The amorphous layer is an antifuse and is electrically and irreversibly switchable from high resistance state to low resistance state.
Inventors
- 👤 William Turlay Stacy
- 👤 Sheldon Chil Pin Lim
- 👤 Kevin Gene-Wah Jew
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10P; H10P95/00; H10P95/80; Y; Y10; Y10S; Y10S148/00; Y10S148/055
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
208 words
A semiconductor memory structure, comprising: (a) a semiconductor body having a surface layer of first type conductivity; (b) a first region of second type conductivity formed in a selected portion of said surface layer to produce a semiconductive junction with said surface layer; (c) a second region formed in said first region and extending to the surface of said surface layer; (d) a third region of first type conductivity formed in a selected portion of said surface layer laterally spaced from said first and second regions, said third region being heavily doped to have a higher conductivity than said surface layer; and (e) a buried layer of first type conductivity extending into said surface layer and beneath both said third region and said first and second regions, said buried layer being heavily doped to form a low resistance path between said third region and semiconductive junction; said surface layer, said first region, said third region, and said buried layer being crystalline in form, said second region being amorphous in form and irreversibly switchable from a high resistive to a low resistive state upon application of a bias voltage of predetermined magnitude applied in the forward direction of said semiconductive junction between said second region and said third region.
Claim 2
Dependent Claim
208 words
A semiconductor memory structure, comprising: (a) a semiconductor body having a surface layer of first type conductivity; (b) a first region of second type conductivity formed in a selected portion of said surface layer to produce a semiconductive junction with said surface layer; (c) a second region formed in said first region and extending to the surface of said surface layer; (d) a third region of first type conductivity formed in a selected portion of said surface layer laterally spaced from said first and second regions, said third region being heavily doped to have a higher conductivity than said surface layer; and (e) a buried layer of first type conductivity extending into said surface layer and beneath both said third region and said first and second regions, said buried layer being heavily doped to form a low resistance path between said third region and semiconductive junction; said surface layer, said first region, said third region, and said buried layer being crystalline in form, said second region being amorphous in form and irreversibly switchable from a high resistive to a low resistive state upon application of a bias voltage of predetermined magnitude applied in the forward direction of said semiconductive junction between said second region and said third region.
Claim 3
Dependent Claim
27 words
The invention according to claim 1 and further including a locally oxidized region of said surface layer separating said third region from said first and second regions.
Claim 4
Dependent Claim
19 words
The invention according to claim 1, wherein said semiconductive junction lies wholly beneath the surface of said surface layer.
Claim 5
Dependent Claim
24 words
The invention according to claim 3, wherin the interface between said first and second regions lies wholly beneath the surface of said surface layer.
Claim 6
Dependent Claim
15 words
The invention according to claim 1, wherein said surface layer is made of monocrystalline silicon.
Claim 7
Dependent Claim
33 words
The invention according to claim 5 and further including a substrate of second type conductivity upon which said surface layer is formed by epitaxial deposition; said buried layer extending also into said substrate.
Claim 8
Dependent Claim
12 words
The invention according to claim 6, wherein said substrate is P type.
Claim 9
Dependent Claim
176 words
A semiconductive memory structure, comprising; (a) a semiconductor body portion of first type conductivity having a surface; (b) a first region of second type conductivity formed in said body portion and lying beneath said surface and forming a semiconductive junction with an adjoining part of said body portion; said body portion and said first region having a monocrystalline structure, and (c) coupling means including first and second contact means applied to said body portion, said first contact means being present above said first region and said second contact means being present at a region spaced from said first region characterized in that in said first region a second region is present which extends to said surface said second region having an amorphous structure and being capable of irreversible transition from high resistance form to low resistance form upon application of predetermined electrical voltage bias in its thickness direction, said second contact means being applied to said second region and said coupling means coupling said first and second regions and said semiconductive junction in electricial series circuit.
Claim 10
Dependent Claim
176 words
A semiconductive memory structure, comprising; (a) a semiconductor body portion of first type conductivity having a surface; (b) a first region of second type conductivity formed in said body portion and lying beneath said surface and forming a semiconductive junction with an adjoining part of said body portion; said body portion and said first region having a monocrystalline structure, and (c) coupling means including first and second contact means applied to said body portion, said first contact means being present above said first region and said second contact means being present at a region spaced from said first region characterized in that in said first region a second region is present which extends to said surface said second region having an amorphous structure and being capable of irreversible transition from high resistance form to low resistance form upon application of predetermined electrical voltage bias in its thickness direction, said second contact means being applied to said second region and said coupling means coupling said first and second regions and said semiconductive junction in electricial series circuit.
Claim 11
Dependent Claim
22 words
The invention according to claim 8, wherein said semiconductor body portion is made of silicon and said second region is anorphous silicon.
Claim 12
Dependent Claim
15 words
The invention according to claim 9, wherein said second region is an ion implanted region.
Claim 13
Dependent Claim
77 words
The invention according to claim 8, and further including a third region in said body portion spaced laterally from said first and second regions, and a buried layer of heavy doping concentration of first type conductivity forming with said third region part of the coupling means and lying at least partly in said body portion in a region beneath said semiconductive junction and extending laterally in said body portion so as to lie beneath said third region.
Claim 14
Dependent Claim
27 words
The invention according to claim 11, wherein said third region is of the same type conductivity as said body portion and of higher doping concentration relative thereto.
Claim 15
Dependent Claim
20 words
The invention according to claim 9 wherein the contact means applied to said second region comprises a metallic silicide alloy.
Claim 16
Dependent Claim
24 words
The invention according to claim 13 wherein the silicide alloy is selected from the group consisting of platinum silicide, platinel silicide and palladium silicide.
Claim 17
Independent Claim
165 words
A method of fabricating a semiconductive programmable read only memory structure, comprising: (a) locally oxidizing selected surface regions of a body portion of crystalline semiconductor material of first type conductivity to produce a plurality of laterally isolated semiconductor regions in said body portion; (b) introducing dopant impurities of second type conductivity in a first one of said isolated semiconductor regions to produce a first region of second type conductivity forming a semiconductive junction with said body portion at a location beneath the surface of said body portion (c) implanting ions of sufficiently high energy and density within a surface layer of said first region to convert said surface layer to amorphous form that is electrically and irreversibly switchable from high resistance state to low resistance state; and (d) introducing dopant impurities of first type conductivity in a second one of said isolated semiconductor regions lying adjacent to said first isolated region to form a low resistance contact region at the surface of said body portion.
Claim 18
Independent Claim
165 words
A method of fabricating a semiconductive programmable read only memory structure, comprising: (a) locally oxidizing selected surface regions of a body portion of crystalline semiconductor material of first type conductivity to produce a plurality of laterally isolated semiconductor regions in said body portion; (b) introducing dopant impurities of second type conductivity in a first one of said isolated semiconductor regions to produce a first region of second type conductivity forming a semiconductive junction with said body portion at a location beneath the surface of said body portion (c) implanting ions of sufficiently high energy and density within a surface layer of said first region to convert said surface layer to amorphous form that is electrically and irreversibly switchable from high resistance state to low resistance state; and (d) introducing dopant impurities of first type conductivity in a second one of said isolated semiconductor regions lying adjacent to said first isolated region to form a low resistance contact region at the surface of said body portion.
Claim 19
Dependent Claim
37 words
A method according to claim 15 and further including forming a low resistance semiconductor region of first type conductivity within said body portion spaced from and lying beneath said semiconductive junction and said low resistance contact region.
Claim 20
Dependent Claim
21 words
A method according to claim 15 wherein said impurity ions in step (c) are ions of neutral conductivity in the semiconductor.
Claim 21
Dependent Claim
18 words
A method according to claim 15 wherein said impurity ions in step (c) are of second type conductivity.
Claim 22
Dependent Claim
16 words
A method according to claim 15 wherein said semiconductor body is lightly doped N type silicon.
Claim 23
Dependent Claim
26 words
A method according to claim 15 wherein the impurity ions in step (c) are implanted with an energy substantially in the range of 10Kev to 180Kev.
Claim 24
Dependent Claim
27 words
A method according to claim 15 wherein the impurity ions in step (c) have a dose of 1 x 10 15 ions per square centimeter or greater.
Claim 25
Dependent Claim
15 words
A method according to claim 21 wherein the impurity ions in step (c) are argon.
References Cited (Backward Citations)
No citation records indexed.
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