EP0118053A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Image signal processor
Assignee: Hitachi Ltd
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Filing: 1984-02-08
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Granted: —
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Expires: 2004-02-08
Abstract
Abstract A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing density image processing technique has been developed. An architecture of the image signal processor (ISP) which can process a density image having 256 tones at a video rate (256 x 256 image, 6MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighbourhood operation, is disclosed. The image signal processor (ISP) is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements (PE's) as that of input pixel data used to produce one output pixel data.
Inventors
- 👤 Tadashi Fukushima
- 👤 Yoshiki Kobayashi
- 👤 Yoshiyuki Okuyama
- 👤 Takeshi Katoh
- 👤 Seiji Kashioka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 06:45
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
219 words
An image signal processor comprising: a first port (Pl) for receiving an image data; a data unit (101) for shifting said image data by a plurality of stages and parallelly transferring the image data at respective shift stages to a processor unit (103); a second port (P2) for externally outputting the image data serially transferred from said data unit; a third port (P3) for receiving a basic data for image processing, a control data for designating an operation function and the image data or an image processing data; a control unit (106) for receiving said control data through said third port and a timing signal and outputting a command signal necessary for control; a memory unit (102) for storing said basic data supplied form said third port in accordance with the command signal from said control unit and outputting the stored data to said processor unit in accordance with the command signal; said processor unit (103) having a plurality of processor elements for processing simultaneously the image based on the input image data; a linkage unit (104) for receiving an operation result of said processor and the data through said third port for carrying out a linkage operation; and a fourth port (P4) for receiving an operation result of said linkage unit and externally outputting the input data thereto.
Claim 2
Dependent Claim
219 words
An image signal processor comprising: a first port (Pl) for receiving an image data; a data unit (101) for shifting said image data by a plurality of stages and parallelly transferring the image data at respective shift stages to a processor unit (103); a second port (P2) for externally outputting the image data serially transferred from said data unit; a third port (P3) for receiving a basic data for image processing, a control data for designating an operation function and the image data or an image processing data; a control unit (106) for receiving said control data through said third port and a timing signal and outputting a command signal necessary for control; a memory unit (102) for storing said basic data supplied form said third port in accordance with the command signal from said control unit and outputting the stored data to said processor unit in accordance with the command signal; said processor unit (103) having a plurality of processor elements for processing simultaneously the image based on the input image data; a linkage unit (104) for receiving an operation result of said processor and the data through said third port for carrying out a linkage operation; and a fourth port (P4) for receiving an operation result of said linkage unit and externally outputting the input data thereto.
Claim 3
Dependent Claim
139 words
An image signal processing LSI comprising: a control unit (106) for receiving an external control signal; a first input port (Pl) for receiving a data to be processed in said LSI; a second input port (P2); a third input port (P3); a data unit (101) for converting data inputted to said first input port and said second input port to a parallel data; a processor unit (103) for parallelly processing said input data and said converted data based on an operation data from a self-contained memory; a linkage unit (104) for linking an input data to said third input port and the parallelly processed data; said second port being used as an output port of said LSI; said LSI being connected by said first, second and third input ports and said output port to carry out a parallel operation.
Claim 4
Dependent Claim
139 words
An image signal processing LSI comprising: a control unit (106) for receiving an external control signal; a first input port (Pl) for receiving a data to be processed in said LSI; a second input port (P2); a third input port (P3); a data unit (101) for converting data inputted to said first input port and said second input port to a parallel data; a processor unit (103) for parallelly processing said input data and said converted data based on an operation data from a self-contained memory; a linkage unit (104) for linking an input data to said third input port and the parallelly processed data; said second port being used as an output port of said LSI; said LSI being connected by said first, second and third input ports and said output port to carry out a parallel operation.
Claim 5
Dependent Claim
119 words
An image signal processing LSI according to Claim 2, further comprising: a first path for supplying the data inputted from said first input port and said second input port to said processor unit through respective delay circuits; a second path for supplying the data inputted from said second input port directly to said processor unit and supplying the data inputted from said first input port to said processor unit through some delay circuits; a third path for supplying the data inputted from said third input port, said first input port and said second input port directly to said processor unit; whereby the data are inputted through said some paths in accordance with the control signal from said control unit.
Claim 6
Dependent Claim
65 words
An image signal processing LSI according to Calim 2 wherein said processor unit has a plurality of processor elements (PEO- P E3) and stores operation data supplied from said third input port in said self-contained memory in accordance with the control signal from said control unit and supplies the operation data from said memory directly to said processor elements to carry out a parallel operation.
Claim 7
Dependent Claim
65 words
An image signal processing LSI according to Calim 2 wherein said processor unit has a plurality of processor elements (PEO- P E3) and stores operation data supplied from said third input port in said self-contained memory in accordance with the control signal from said control unit and supplies the operation data from said memory directly to said processor elements to carry out a parallel operation.
Claim 8
Dependent Claim
54 words
An image signal processing LSI according to Claim 2 wherein said linkage unit and said processor unit form pipeline stages by a register driven in synchronism with an operation execution signal outputted in an operation execution mode and/or a set-up signal outputted in a set-up mode, of the control signal from said control unit.
Claim 9
Dependent Claim
54 words
An image signal processing LSI according to Claim 2 wherein said first input port, said second input port, said third input port, said data unit, said processor unit and said linkage unit are programmably configured by storing the data supplied from said control unit in said set-up mode in said self-contained random access memory.
Claim 10
Dependent Claim
21 words
. An image signal processing LSI according to Claim 3 wherein portions of said delay circuits are variable stage shift registers.
Claim 11
Dependent Claim
55 words
An image signal processing LSI according to Claim 4 wherein said operation data is supplied to said processor elements one byte at a time when said LSI carries out a primary differentiation operation, and two bytes at a time, including one byte for designating an image processing area when said LSI processes a binary image.
Claim 12
Dependent Claim
41 words
An image signal processing LSI according to Claim 2 wherein said second input port includes a tri-state buffer so that it can be functioned as the output port by an input/output direction signal of the control signal from said control unit.
Claim 13
Dependent Claim
81 words
An image signal processing LSI according to Claim 6 wherein a predetermined data from said third input port is stored in a control register in said control unit in said set-up mode, a command necessary for said program is generated based on said stored data and an input data externally supplied to said control unit to determine functions of said first input port, said second input port, said third input port, said data unit, said processor unit and said linkage unit.
References Cited (Backward Citations)
No citation records indexed.
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