Electrical circuit comprising a hybrid power switching semiconductor device including an SCR structure

Claim 2

An IGR/SCR hybrid power switching semiconductor device having a predetermined operating current range extending from zero current up to a maximum current, and having a mode crossover current point within the operating current range, said device comprising: a body of semiconductor material including, in succession therein, anode, first base, second base, and cathode regions, said cathode and first base regions being of one conductivity type, and the anode and second base regions being of opposite conductivity type; a channel portion within said second base region and extending into said second base region from a channel surface contiguous with a surface of said body, said cathode and first base regions being spaced from each other to define the extent of said channel portion therebetween; an insulated gate electrode over said channel surface configured for inducing in said channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said cathode region and said first base region; a cathode terminal electrode contacting said cathode region; an anode terminal electrode contacting said anode region; said first and second base regions, said anode regions and said cathode region being configured and arranged such that, for operating currents below the mode crossover current point, said device functions as an insulated-gate rectifier which conduction in a forward direction when the conduction channel is induced and ceases to support forward conduction when the conduction channel is no longer induced, and such that, for operating currents above the mode crossover current point, said device functions as a thyristor which latches into a forward conduction mode once triggered by a voltage applied to said insulated gate electrode.

Claim 3

An IGR/SCR hybrid device in accordance with Claim 1, wherein said cathode terminal electrode additionally contacts said second base region to provide a cathode short between said cathode and second base regions, and the mode crossover current point is determined in part by the contact area of said cathode electrode with said second base region relative to the overall cathode terminal electrode contact area.

Claim 4

An IGR/SCR hybrid device in accordance with Claim 2, wherein the contact area of said cathode electrode with said second base region relative to the overall cathode terminal electrode contact area is selected such that said mode crossover current point is in the order of one ampere.

Claim 5

An electrical circuit comprising: i an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; and an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure electrically connected to said electrical load device for controlling energization thereof; said parasitic PNPN thyristor structure of said insulated-gate rectifier having a holding current rating, and said insulated-gate rectifier being configured and arranged such that the holding current rating is less than the inrush current of said load device and greater than the operating current of I said load device.

Claim 6

An electrical circuit comprising: i an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; and an insulated-gate rectifier of the type including a parasitic PNPN thyristor structure electrically connected to said electrical load device for controlling energization thereof; said parasitic PNPN thyristor structure of said insulated-gate rectifier having a holding current rating, and said insulated-gate rectifier being configured and arranged such that the holding current rating is less than the inrush current of said load device and greater than the operating current of I said load device.

Claim 7

An electrical circuit in accordance with Claim 4, wherein said electrical load device comprises a lamp filament.

Claim 8

An electrical circuit comprising: an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter: and an insulated-gate rectifier having a pair of main terminals and a control gate terminal, and being of the type including a parasitic PNPN thyristor structure, the main terminals of said insulated-gate rectifier being electrically connected to said electrical load device for controlling energization thereof; said insulated-gate rectifier being configured and arranged such that, when the relatively higher inrush current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is latched into a conducting state uncontrollable by means of the control gate terminal, and such that, when the relatively lower operating current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is not latched into a conducting state, whereby conduction through said insulated-gate rectifier is controllable by means of the control gate terminal.

Claim 9

An electrical circuit comprising: an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter: and an insulated-gate rectifier having a pair of main terminals and a control gate terminal, and being of the type including a parasitic PNPN thyristor structure, the main terminals of said insulated-gate rectifier being electrically connected to said electrical load device for controlling energization thereof; said insulated-gate rectifier being configured and arranged such that, when the relatively higher inrush current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is latched into a conducting state uncontrollable by means of the control gate terminal, and such that, when the relatively lower operating current flows through said insulated-gate rectifier, the parasitic PNPN thyristor is not latched into a conducting state, whereby conduction through said insulated-gate rectifier is controllable by means of the control gate terminal.

Claim 10

An electrical circuit in accordance with Claim 6, wherein said electrical load device comprises a lamp filament.

Claim 13

A method in accordance with Claim 8, which comprises utilizing the insulated-gate rectifier to control energization of an electrical load device of the type which draws a relatively higher inrush current when initially energized and a relatively lower operating current thereafter; the inrush current of the load device being at least as great as the holding current rating of the parasitic PNPN thyristor structure, and the operating current of the load device j being less than the holding current rating of the parasitic PNPN thyristor structure.

Claim 14

A method in accordance with Claim 9, which comprises utilizing the insulated-gate rectifier to control energization of a lamp filament.

Claim 15

An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a i field-effect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said field-effect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; a first main terminal region layer heavily-doped to the opposite conductivity type, said first main terminal region layer being common to both said field-effect transistor portion and said thyristor portion, said first main terminal region layer being contiguous with said first base layer second portion within said thyristor portion, and said first main terminal region layer extending to said first principal surface; a buried layer heavily-doped to the one conductivity type included in said field-effect transistor portion between said first base layer first portion and said first main terminal region layer, and not within said thyristor portion between said first base layer second portion and said first main terminal region; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; second main terminal region first and second portions of the one conductivity type, said second main terminal region j first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; first and second channel portions, said first channel portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion and said first base layer first portion being spaced to define the extent of said first channel portion therebetween, and said second channel portion being included in said thyristor portion within said second base region second portion, said second main terminal region second portion and said first base layer second portion being spaced to define the extent of said second channel portion therebetween; and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region. ;

Claim 16

An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a i field-effect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said field-effect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; a first main terminal region layer heavily-doped to the opposite conductivity type, said first main terminal region layer being common to both said field-effect transistor portion and said thyristor portion, said first main terminal region layer being contiguous with said first base layer second portion within said thyristor portion, and said first main terminal region layer extending to said first principal surface; a buried layer heavily-doped to the one conductivity type included in said field-effect transistor portion between said first base layer first portion and said first main terminal region layer, and not within said thyristor portion between said first base layer second portion and said first main terminal region; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; second main terminal region first and second portions of the one conductivity type, said second main terminal region j first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; first and second channel portions, said first channel portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion and said first base layer first portion being spaced to define the extent of said first channel portion therebetween, and said second channel portion being included in said thyristor portion within said second base region second portion, said second main terminal region second portion and said first base layer second portion being spaced to define the extent of said second channel portion therebetween; and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region. ;

Claim 17

A hybrid semiconductor device in accordance with Claim 11, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise portions of the same second base region.

Claim 18

A hybrid semiconductor device in accordance with Claim 11, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise individual island-like second base regions spaced from each other within said first base layer.

Claim 19

A hybrid semiconductor device in accordance with Claim 11, wherein: said first base region is of N conductivity type; said second base region is of P conductivity type; said first main terminal region layer is of P conductivity type and comprises an anode region of said device; and said second main terminal region is of N conductivity type and comprises a cathode region of said device.

Claim 20

An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a field-effect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said field- effect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a ; second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; a first main terminal region layer first portion heavily-doped to the one conductivity type included in said field-effect transistor portion, said first main terminal region first portion being contiguous with said first base layer first portion within said field-effect transistor portion and extending to said first principal surface; a first main terminal region layer second portion heavily-doped to the opposite conductivity type included in said thyristor portion, said first main terminal region layer second portion being contiguous with said first base layer second portion within said thyristor portion and extending to said first principal surface; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; second main terminal region first and second portions of the one conductivity type, said second main terminal region first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; first and second channel portions, said first channel portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion and said first base layer first portion being spaced to define the extent of said first-channel portion therebetween, and said second channel portion being included in said thyristor portion within said second base region second portion, said second main terminal region second portion and said first base layer second portion being spaced to define the extent of said second channel portion therebetween; and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region.

Claim 21

An IGFET/insulated-gate-triggered thyristor hybrid power switching semiconductor device comprising: a body of semiconductor material including a field-effect transistor portion and a thyristor portion, said body having first and second opposed principal surfaces on opposite sides of said body; a first base layer of one conductivity type, said first base layer having a first portion included in said field- effect transistor portion, said first base layer first portion comprising a drift region, and said first base layer having a ; second portion included in said thyristor portion, said first base layer second portion comprising an active-base region; a first main terminal region layer first portion heavily-doped to the one conductivity type included in said field-effect transistor portion, said first main terminal region first portion being contiguous with said first base layer first portion within said field-effect transistor portion and extending to said first principal surface; a first main terminal region layer second portion heavily-doped to the opposite conductivity type included in said thyristor portion, said first main terminal region layer second portion being contiguous with said first base layer second portion within said thyristor portion and extending to said first principal surface; second base region first and second portions of the opposite conductivity type, said second base region first portion being included in said field-effect transistor portion contiguous with said first base layer first portion, said second base region first portion comprising a shield-base region, and said second base region second portion being included in said thyristor portion and contiguous with said first base layer second portion, said second base region second portion comprising an active-base region; second main terminal region first and second portions of the one conductivity type, said second main terminal region first portion being included in said field-effect transistor portion contiguous with said second base region first portion, and said second main terminal region second portion being included in said thyristor portion contiguous with said second base region second portion; first and second channel portions, said first channel portion being included in said field-effect transistor portion within said second base region first portion, said second main terminal region first portion and said first base layer first portion being spaced to define the extent of said first-channel portion therebetween, and said second channel portion being included in said thyristor portion within said second base region second portion, said second main terminal region second portion and said first base layer second portion being spaced to define the extent of said second channel portion therebetween; and first and second gate electrodes respectively disposed over said first and second channel portions and insulatingly spaced therefrom, said first gate electrode configured for inducing in said first channel portion, when gate voltage is applied thereto, a conduction channel of the one conductivity type extending between said second main terminal region first portion and said first base layer first portion, and said second gate electrode similarly configured for inducing in said second channel portion, when gate voltage is applied thereto, a thyristor conduction-triggering depletion region.

Claim 22

A hybrid semiconductor device in accordance with Claim 15, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise portions of the same second base region.

Claim 23

A hybrid semiconductor device in accordance with Claim 15, wherein said second base region first and second portions respectively included in said field-effect transistor portion and in said thyristor portion comprise individual island-like second base regions spaced from each other within said first base layer.

Claim 24

A hybrid semiconductor device in accordance with Claim 11, wherein: said first base region is of N conductivity type; said second base region is of P conductivity type; said first main terminal region layer is of P conductivity type and comprises an anode region of said device; and said second main terminal is of N conductivity type and comprises a cathode region of said device.