EP0116464A2
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EP
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A semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-02-08
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Granted: —
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Expires: 2004-02-08
Abstract
Abstract A semiconductor memory device comprises a plurality of memory cell blocks (11, 12,......18) corresponding to the output terminals (Q,, Q 2 ,...Q 8 ), respectively, and a redundancy memory cell block (19) for replacing a faulty memory cell block among the memory cell blocks, the redundancy memory cell block having a first specific area (19a) for storing a first predetermined data of electronic signatures, each of the memory cell blocks having a second specific area (11a, 12a,....18a) for storing a second predetermined data equal to a part of the first predetermined data in one by one correspondence. The semiconductor memory device further comprises a means for selectively reading, when one of the memory cell blocks is replaced by the redundancy memory cell block, the part of the first predetermined data corresponding to the second predetermined data stored in the memory cell block to be replaced by the redundancy memory cell block, whereby the second predetermined data can be correctly read out even when a faulty memory cell block is replaced with the redundancy memory cell block.
Inventors
- 👤 Masanobu Yoshida
- 👤 Kiyoshi Itano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 00:22
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835; G11C7/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
164 words
A semiconductor memory device comprising: a plurality of output terminals for outputting a plurality of output bit data, respectively; a plurality of memory cell blocks corresponding to said output terminals, respectively; and a redundancy memory cell block able to replace a faulty memory cell block among said memory cell blocks; said redundancy memory cell block having a first specific area for storing a first predetermined data consisting of a plurality of bits, each of said memory cell blocks having a second specific area for storing a second predetermined data, said second predetermined data being equal to a divided one of said first predetermined data in one by one correspondence, said semiconductor memory device further comprising a means for selectively reading, when one of said memory cell blocks is replaced by said redundancy memory cell block, a divided one of said first predetermined data corresponding to said second predetermined data stored in the memory cell block to be replaced by said redundancy memory cell block.
Claim 2
Dependent Claim
164 words
A semiconductor memory device comprising: a plurality of output terminals for outputting a plurality of output bit data, respectively; a plurality of memory cell blocks corresponding to said output terminals, respectively; and a redundancy memory cell block able to replace a faulty memory cell block among said memory cell blocks; said redundancy memory cell block having a first specific area for storing a first predetermined data consisting of a plurality of bits, each of said memory cell blocks having a second specific area for storing a second predetermined data, said second predetermined data being equal to a divided one of said first predetermined data in one by one correspondence, said semiconductor memory device further comprising a means for selectively reading, when one of said memory cell blocks is replaced by said redundancy memory cell block, a divided one of said first predetermined data corresponding to said second predetermined data stored in the memory cell block to be replaced by said redundancy memory cell block.
Claim 3
Dependent Claim
54 words
A semiconductor memory device as set forth in claim 1, wherein said first specific area in said redundancy memory cell block is divided into a plurality of first sub-blocks, each of said first sub-blocks storing said divided one of said first predetermined data, said divided one corresponding to one of said memory cell blocks.
Claim 4
Dependent Claim
58 words
A semiconductor memory device as set forth in claim 2, wherein said second specific area in each of said memory cell blocks is divided into a plurality of second sub-blocks, at least one of said second sub-blocks in each of said memory cell blocks storing the same data as the data stored in one of said first sub-blocks.
Claim 5
Dependent Claim
38 words
A semiconductor memory device as set forth in claim 3, wherein each of said second sub-blocks in each of said memory cell blocks is storing the same data as the data stored in one of said first sub-blocks.
Claim 6
Dependent Claim
50 words
A semiconductor memory device as set forth in claim 3 or 4, wherein said means comprises an address signal generating circuit for selecting a desired one of said first sub-blocks, said desired one corresponding to one of said memory cell blocks to be replaced by said redundancy memory cell block.
Claim 7
Dependent Claim
76 words
A semiconductor memory device as set forth in claim 5, wherein said means further comprises a plurality of switching circuits corresponding to said memory cell blocks, respectively, each of said switching circuits operatively selecting, when the corresponding memory cell block is to be replaced by said redundancy memory cell block, the output of said redundancy memory cell block in place of the output of said corresponding memory cell block to transfer to said corresponding output terminal.
Claim 8
Dependent Claim
68 words
A semiconductor memory device as set forth in claim 6, wherein said means further comprises a plurality of control signal generating circuits corresponding to said memory cell blocks and to said redundancy memory cell block, respectively, each of said control signal generating circuits operatively generating, when the corresponding memory cell block is to be replaced, a control signal for controlling the switching operation of the corresponding switching circuit.
Claim 9
Dependent Claim
76 words
A semiconductor memory device as set forth in claim 7, wherein said first predetermined area and said second predetermined area include read only memory cells for storing said first and second predetermined data, said read only memory cells operatively being selected by a virtual word line, said means further comprising a signal detecting circuit for selecting said virtual word line in response to a specific address input signal for reading said first or second predetermined data.
Claim 10
Dependent Claim
116 words
A semiconductor memory device as set forth in claim 8, wherein said address signal generating circuit comprises a plurality of address signal determining circuits corresponding to said memory cell blocks, each of said address signal determining circuits operatively determining, in response to said control signal, and when the corresponding memory cell block is to be replaced by said redundancy memory cell block, fixed address signals for accessing one of said first sub-blocks corresponding to one of said memory cell blocks to be replaced, and also comprises a plurality of address signal selecting circuits each for selecting an external address input signal or one of said fixed address signals in response to said specific address input signal.
Claim 11
Dependent Claim
76 words
A semiconductor memory device as set forth in claim 9, wherein said memory cell blocks include erasable and programmable read only memory cells in an area except for said second specific area, and said redundancy memory cell blocks include redundancy memory cells in an area except for said first predetermined area, each of said erasable and programmable read only memory cells and said redundancy memory cells being arranged between a word line and a bit line.
Claim 12
Dependent Claim
40 words
A semiconductor memory device as set forth in claim 10 further comprises a row decoder for selecting one of said word lines, said row decoder operatively being inhibited to select said word lines when said virtual word line is selected.
Claim 13
Dependent Claim
56 words
A semiconductor memory device as set forth in claim 11, wherein said means further comprises a signal detecting circuit for detecting said specific address input signal so as to select said virtual word line, to inhibit the operation of said row decoder and to actuate said address signal selecting circuits to select said fixed address signals.
Claim 14
Dependent Claim
187 words
A memory device comprising: a plurality of memory blocks (11, 12,...18) for storing bit sequences, respective bits of each sequence being stored in different memory blocks of the plurality so that a stored sequence can be read out in parallel form from respective output points (Q 1 , Q 2 ,....Q 8 ) of the memory blocks, the said memory blocks also storing a prerecorded signature data sequence, respective components (D 1 , D 2 ,.....D 8 ) of that sequence being stored in different memory blocks of the plurality; signature reading means, for reading out the said prerecorded signature data sequence; and a redundancy memory block (19), for use in place of any block of the said plurality that may prove faulty; wherein the prerecorded signature data sequence is also stored, in its entirety, in the redundancy memory block and the device is such that when the redundancy memory block is used in place of a faulty block the signature reading means read from the redundancy memory block the component of the prerecorded signature data sequence that would otherwise have been read from the faulty block.
Claim 15
Dependent Claim
187 words
A memory device comprising: a plurality of memory blocks (11, 12,...18) for storing bit sequences, respective bits of each sequence being stored in different memory blocks of the plurality so that a stored sequence can be read out in parallel form from respective output points (Q 1 , Q 2 ,....Q 8 ) of the memory blocks, the said memory blocks also storing a prerecorded signature data sequence, respective components (D 1 , D 2 ,.....D 8 ) of that sequence being stored in different memory blocks of the plurality; signature reading means, for reading out the said prerecorded signature data sequence; and a redundancy memory block (19), for use in place of any block of the said plurality that may prove faulty; wherein the prerecorded signature data sequence is also stored, in its entirety, in the redundancy memory block and the device is such that when the redundancy memory block is used in place of a faulty block the signature reading means read from the redundancy memory block the component of the prerecorded signature data sequence that would otherwise have been read from the faulty block.
References Cited (Backward Citations)
No citation records indexed.
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