EP0115187A2
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EP
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Semiconductor memory device with decoder means
Assignee: Fujitsu Ltd
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Filing: 1983-12-22
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Granted: —
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Expires: 2003-12-22
Abstract
Abstract A semiconductor memory device comprising a plurality of memory cells (MCa) arranged in a matrix form and a decoder circuit (9) for selecting a row of the matrix in response to an address signal (SA). The decoder circuit (9) comprises a first stage decoder (91) including a plurality of first stage decoding elements (G, ... G m ) and a second stage decoder (92) including a plurality of second stage decoding elements (Gl 1 ... GM n ). Each first stage decoding element (G 1 ... G m ) is connected to a plurality of second stage decoding elements (Gl 1 ... Gm n ). Each of the first stage decoding elements (G, ... G m ) receives predetermined higher bits (SA L1 ) of the address signals. One of the first stage decoding elements is thus selected upon one access command. Each of the plurality of second stage decoding elements (Gl 1 ... Gm n ) receives the address signals. One of the rows of the matrix is thus selected in response to the address signals when the corresponding first stage decoding element operates, whereby the power consumption is reduced.
Inventors
- 👤 Yasuro Matsuzaki
- 👤 Toshitaka Fukushima
- 👤 Kouji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 08:28
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C8/12
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
147 words
A semiconductor memory device comprising a plurality of rows of memory cells (MCa); and decoder means for selecting one row of the matrix in response to a corresponding one of a plurality of address signals (SAi), the decoder means comprising a first stage decoder (91) having a plurality of first stage decoding elements (G l ... G m ), each of the first stage decoding elements being connected to a plurality of second stage decoding elements (Gl l ... Gm n ) of a second stage decoder (92), wherein each of the second stage decoding elements (Gl l ... Gm n ) receives the plurality of address signals, and each of the first stage decoding elements (G l ... G m ) receives part of the plurality of address signals, whereby one of the second stage decoding elements causes a row of the matrix to be selected.
Claim 2
Dependent Claim
147 words
A semiconductor memory device comprising a plurality of rows of memory cells (MCa); and decoder means for selecting one row of the matrix in response to a corresponding one of a plurality of address signals (SAi), the decoder means comprising a first stage decoder (91) having a plurality of first stage decoding elements (G l ... G m ), each of the first stage decoding elements being connected to a plurality of second stage decoding elements (Gl l ... Gm n ) of a second stage decoder (92), wherein each of the second stage decoding elements (Gl l ... Gm n ) receives the plurality of address signals, and each of the first stage decoding elements (G l ... G m ) receives part of the plurality of address signals, whereby one of the second stage decoding elements causes a row of the matrix to be selected.
Claim 3
Dependent Claim
80 words
A semiconductor memory device according to claim 1, wherein each of the first stage decoding elements (G1 ... G m ) includes a first gate circuit (7a l , 7a 2 ) receiving part of the address signal (SAhl), and at least one first switching element (8), the first switching element (8) being turned on when an output of the gate circuit is high to supply power to the corresponding second stage decoding elements (Gl l ... Gm n ).
Claim 4
Dependent Claim
20 words
A semiconductor memory device according to claim 2, wherein the first gate circuit comprises a plurality of diodes (7a1, 7a2).
Claim 5
Dependent Claim
18 words
A semiconductor memory device according to claim 3, in which the diodes (7a1, 7a2) are Schottky barrier diodes.
Claim 6
Dependent Claim
84 words
A semiconductor memory device according to claim 1, wherein each of the first stage decoding elements (G 1 ... G m ) includes a multi-emitter transistor (T 1 ) receiving part of the address signal (SA L1 ) at the emitters, and a first switching element (8), the first switching element (8) being turned on when a collector potential of the multi-emitter transistor (T 1 ) is high to supply power to the corresponding second stage decoding elements (Gl l ... Gm n ).
Claim 7
Dependent Claim
24 words
A semiconductor memory device according to any of claims 2 to 5, wherein the or each first switching element (8) comprises an npn transistor.
Claim 8
Dependent Claim
152 words
A semiconductor memory device according to any of the preceding claims, wherein each of the second stage decoding elements (Gl l ... Gm n ) includes at least one second gate circuit (1a1) receiving the remaining part of the plurality of address signals (SA L1 ), the output of the second gate circuit being connected to the output of the respective first stage decoding element (G 1 ... G m ), and at least one second switching element (12) having a trigger terminal connected to the output of the respective first stage decoding element (G 1 ... G m ), the output of the second switching element (Gl l ... Gm n ) selecting one of the rows of memory cells when the output of the corresponding first stage decoding element (G 1 ... G m ) is high and the output of the second gate circuit (1a 1 ) is high.
Claim 9
Dependent Claim
24 words
A semiconductor memory device according to claim 7, wherein the second gate circuit (1a 1 ) comprises a plurality of diodes (111a - 111c).
Claim 10
Dependent Claim
18 words
A semiconductor memory device according to claim 8, wherein the diodes (111a - 111c) are Schottky barrier diodes.
Claim 11
Dependent Claim
159 words
A semiconductor memory device according to any of claims 1 to 6, wherein each of the second stage decoding elements (G l ... G m ) includes at least one multi- emitter transistor (T 2 ) receiving the remaining part of the plurality of address signals (SA L1 ) at the emitters, the output of the multi-emitter transistor (T 2 ) being connected to the output of the respective first stage decoding element (G l ... G m ), and at least one second switching element (T 3 ) having a trigger terminal connected to the output of the respective first stage decoding element (G l ... G m ), the output of the second switching element (T 3 ) selecting one of the rows of the matrix when the output of the corresponding first stage decoding element (G l ... G m ) is high and the collector potential of the multi-emitter transistor (T 2 ) is high.
Claim 12
Dependent Claim
36 words
A semiconductor memory device according to any of claims 7 to 10, wherein the or each second switching element (12, T 3 ) in the decoding elements of the second stage decoder comprises an npn transistor.
Claim 13
Dependent Claim
72 words
A semiconductor memory device according to any of claims 7 to 10, wherein each decoding element of the second stage decoder (Gl l ... Gm n ) further includes a third gate circuit (1a3) receiving the part of the address signals fed to the corresponding first stage decoding elements (G 1 ... G m ), the output of the third gate circuit being connected to the output of the second gate circuit.
Claim 14
Dependent Claim
22 words
A semiconductor memory device according to claim 12, wherein the third gate circuit comprises a plurality of diodes (17a, 17a 2 ).
Claim 15
Dependent Claim
19 words
A semiconductor memory device according to claim 13, wherein the diodes (17a, 17a 2 ) are Schottky barrier diodes.
Claim 16
Dependent Claim
42 words
A semiconductor memory device according to claim 11, wherein the part of the address signals fed to the corresponding first stage decoding elements (G 1 ... G m ) is fed to emitters of the or each multi-emitter transistor (T 2 ).
References Cited (Backward Citations)
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