EP0115179A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Virtual memory address translation mechanism with combined hash address table and inverted page table
Assignee: International Business Machines Corp
•
Filing: 1983-12-22
•
Granted: —
•
Expires: 2003-12-22
Abstract
Abstract A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.
Inventors
- 👤 Phillip Doyce Hester
- 👤 Richard Ormond Simpson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 08:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G06F11/0781; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F12/14; G06F12/1458; G06F12/1466; G06F12/1475; G06F2212/00; G06F2212/68; G06F2212/683
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
159 words
In a data processing system including a CPU and a large hierachial memory having page frames and means for converting virtual memory addresses supplied by said CPU into real memory addresses within said page frames wherein said real memory space is substantially smaller than said virtual memory scope, the improvement wherein said virtual address converting means comprise means for hashing a selected virtual address to produce a hashed address a combined table in said memory including a first list of the respective virtual address of each real memory address, and a second list connecting each hashed address with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address, means for sequentially searching through said linked group in said table until said selected virtual address is located, and means responsive to said location for accessing from said first list, the real memory address of said located virtual address.
Claim 2
Dependent Claim
159 words
In a data processing system including a CPU and a large hierachial memory having page frames and means for converting virtual memory addresses supplied by said CPU into real memory addresses within said page frames wherein said real memory space is substantially smaller than said virtual memory scope, the improvement wherein said virtual address converting means comprise means for hashing a selected virtual address to produce a hashed address a combined table in said memory including a first list of the respective virtual address of each real memory address, and a second list connecting each hashed address with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address, means for sequentially searching through said linked group in said table until said selected virtual address is located, and means responsive to said location for accessing from said first list, the real memory address of said located virtual address.
Claim 3
Dependent Claim
43 words
The data processing system of claim 1 wherein said virtual address converting means further include means for storing a combined base address for said table including the base address for said first list in combination with the base address for said second list.
Claim 4
Dependent Claim
45 words
The data processing system of claim 2 wherein said virtual address converting means further includes means for accessing said predetermined initial address of a linked group in said second list by calculating the offset from said stored table base address based upon said hashed address.
Claim 5
Dependent Claim
53 words
The data processing system of claim 2 wherein the virtual addresses in each linked group are respectively connected by linking addresses, and said virtual address converting means further includes means for accessing virtual addresses in said first list by calculating the offset from said stored table base address based upon said linking address.
Claim 6
Dependent Claim
161 words
In a data processing system including a CPU and a large hierachial memory having page frames and means for converting virtual memory addresses supplied by said CPU into real memory addresses within said page frames wherein said real memory space is substantially smaller than said virtual memory scope, and wherein said virtual address converting means comprise a combined table in said memory including a first list of the respective virtual address of each real memory address, and a second list connecting each hashed address with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produce the connected hashed address, an improved method for converting said virtual memory addresses into real memory addresses comprising hashing a selected virtual memory address, sequentially searching through said linked group in said table until said selected virtual address is located, and upon said location, accessing from said first list, the real memory address of said located virtual address.
Claim 7
Dependent Claim
161 words
In a data processing system including a CPU and a large hierachial memory having page frames and means for converting virtual memory addresses supplied by said CPU into real memory addresses within said page frames wherein said real memory space is substantially smaller than said virtual memory scope, and wherein said virtual address converting means comprise a combined table in said memory including a first list of the respective virtual address of each real memory address, and a second list connecting each hashed address with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produce the connected hashed address, an improved method for converting said virtual memory addresses into real memory addresses comprising hashing a selected virtual memory address, sequentially searching through said linked group in said table until said selected virtual address is located, and upon said location, accessing from said first list, the real memory address of said located virtual address.
Claim 8
Dependent Claim
73 words
6. The method of claim 5 wherein said virtual address converting means further include means for storing a combined base address for said table including the base address for said first list in combination with the base address for said second list, and said method accesses said predetermined initial address of a linked group in said second list by calculating the offset from said stored table base address based upon said hashed address.
Claim 9
Dependent Claim
81 words
7. The method of claim 5 wherein said virtual address converting means further include means for storing a combined base address for said table including the base address for said first list in combination with the base address for said second list, and the virtual addresses in each linked group are respectively connected by linking addresses, and said method accesses virtual addresses in said first list by calculating the offset from said stored table base address based upon said linking address.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.