Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
311 words
A semiconductor memory device comprising a plurality of column lines (6 0 to 6q); a plurality of row lines (7 0 to 7p); a column decoder (10) connected to the column lines (6 0 to 6q) for selecting one of the column lines (6 0 to 6q); a row decoder (11) connected to the row lines (7 0 to 7p) for selecting one of the row lines (7 0 to 7p); a plurality of memory cells (2 00 to 2 pq , 3 00 to 3pq) one of which is accessed by means of a selected column line and a selected row line; a clock generator (24) for producing clock pulses; a voltage supply (17) for supplying a high voltage; and a plurality of charge pump circuits (12 0 to 12 q , 13 0 to 13p) each of which is connected to one of the column lines (6 0 to 6 q ) and the row lines (7 0 to 7p), respectively, and is connected to the clock generator (24), for increasing the voltage on the selected column and row lines up to the high voltage during writing and/or erasing operations, each of the charge pump circuits (12 0 to 12 q , 13 0 to 13p) including a capacitor (20) for charging and discharging in response to the clock pulses, and a charge transfer transistor (22) connected to the capacitor (20), for transferring charge from the voltage supply (17) to the column or row line connected thereto, in response to the voltage on the capacitor (20); characterised in that each charge pump circuit (12 0 to 12q, 13 0 to 13p) comprises gate means connected between the clock generator (24) and the capacitor (20), for disconnecting from the clock generator the capacitor (20) in the charge pump circuit connected to an unselected column line or an unselected row line.
Claim 2
Dependent Claim
311 words
A semiconductor memory device comprising a plurality of column lines (6 0 to 6q); a plurality of row lines (7 0 to 7p); a column decoder (10) connected to the column lines (6 0 to 6q) for selecting one of the column lines (6 0 to 6q); a row decoder (11) connected to the row lines (7 0 to 7p) for selecting one of the row lines (7 0 to 7p); a plurality of memory cells (2 00 to 2 pq , 3 00 to 3pq) one of which is accessed by means of a selected column line and a selected row line; a clock generator (24) for producing clock pulses; a voltage supply (17) for supplying a high voltage; and a plurality of charge pump circuits (12 0 to 12 q , 13 0 to 13p) each of which is connected to one of the column lines (6 0 to 6 q ) and the row lines (7 0 to 7p), respectively, and is connected to the clock generator (24), for increasing the voltage on the selected column and row lines up to the high voltage during writing and/or erasing operations, each of the charge pump circuits (12 0 to 12 q , 13 0 to 13p) including a capacitor (20) for charging and discharging in response to the clock pulses, and a charge transfer transistor (22) connected to the capacitor (20), for transferring charge from the voltage supply (17) to the column or row line connected thereto, in response to the voltage on the capacitor (20); characterised in that each charge pump circuit (12 0 to 12q, 13 0 to 13p) comprises gate means connected between the clock generator (24) and the capacitor (20), for disconnecting from the clock generator the capacitor (20) in the charge pump circuit connected to an unselected column line or an unselected row line.
Claim 3
Dependent Claim
70 words
A device as claimed in Claim 1, characterised in that the gate means includes a transistor (23)connected between the clock generator (24) and the capacitor (20), the transistor (23) being on when the column or row line connected to the charge pump circuit of the gate means is selected and being off when the column or row line connected to the charge pump circuit of the gate means is unselected.
Claim 4
Dependent Claim
41 words
A device as claimed in Claim 2, characterised in that the transistor (23) in each charge pump circuit has a gate electrode connected to the column or row line which is connected to the charge pump circuit of the transistor (23).
Claim 5
Independent Claim
36 words
A device as claimed in any preceding claim, characterised in that the column and row decoders (10,11) supply a source voltage to the selected column and row lines and ground the unselected column and row lines.
Claim 6
Independent Claim
89 words
A device as claimed in any preceding claim, characterised by a plurality of transistors (14 0 to 14 , 15 0 to 15p) connected between the column decoder (10) and the column lines (6 0 to 6q) and between the row decoder (11) and the row lines (7 0 to 7p), said transistors being off only when the column line and the row line connected thereto are selected during writing and erasing operations to disconnect the selected column and row lines from the column and row decoders (10,11), respectively.
Claim 7
Independent Claim
52 words
A device as claimed in any preceding claim, characterised in that each of the memory cells (2 00 to 2 pq , 3 00 to 3 pq ) ) includes a selection transistor used for selection of the memory cells, and a memory transistor connected to the selection transistor for storing information.