Microcomputer

Claim 2

A computer comprising a processor and memory, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor, the function being one of a set of selectable functions, wherein: (a) said processor includes: (i) a plurality of registers providing data holding means and data transfer means for use in data transfers to and from said registers, (ii) means for receiving each instruction and loading into selected data holding means a value associated with the instruction, and (iii) control means for controlling said data transfer means and registers and responsive to said function bits to cause the processor to operate in accordance with said function bits,and (b) said function set includes at least one prefixing function and other functions, the said control means being arranged to cause the said value associated with an instruction including a prefixing function to be loaded into data holding means at a position of different significance than when associated with an instruction having a said other function, and thereby permit loading into the data holding means a plurality of values which are derived from separate instructions to accumulate a value of variable bit length.

Claim 3

A computer comprising a processor and memory, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor, the function being one of a set of selectable functions, wherein: (a) said processor includes: (i) a plurality of registers and data transfer means for use in data transfers to and from said registers, (ii) means for receiving said instruction and loading into one of the processor registers a value associated with the instruction, the said one of the processor registers having a bit length greater than the bit length of the said value, and (iii) control means for controlling said data transfer means and registers and responsive to said function bits to cause the processor to operate in accordance with said function bits, and (b) said function set includes at least one prefixing function and other functions the said control means being responsive to a prefixing function to cause said value associated with an instruction having a prefixing function to be loaded into said one of the processor registers at a position of different significance than when associated with an instruction having a said other function whereby a plurality of values derived from separate instructions may be loaded into said one of the processor registers to accumulate a value of variable bit length.

Claim 4

A computer comprising a processor and memory, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a function to be executed by the processor, the function being one of a set of selectable functions, wherein: (a) said processor includes: (i) a plurality of registers and data transfer means for use in data transfers to and from said registers, (ii) means for receiving said instruction and loading into one of the processor registers a value associated with the instruction, the said one of the processor registers having a bit length greater than the bit length of the said value, and (iii) control means for controlling said data transfer means and registers and responsive to said function bits to cause the processor to operate in accordance with said function bits, and (b) said function set includes at least one prefixing function and other functions the said control means being responsive to a prefixing function to cause said value associated with an instruction having a prefixing function to be loaded into said one of the processor registers at a position of different significance than when associated with an instruction having a said other function whereby a plurality of values derived from separate instructions may be loaded into said one of the processor registers to accumulate a value of variable bit length.

Claim 5

A computer according to claim 2 wherein the means for loading said value into the said one of the processor registers is arranged to load the value into a predetermined set of bit positions within the register and said control means is arranged to transfer the contents of said predeteremined set of bit positions to bit positions of different significance in response to a prefixing function thereby permitting the addition of a further value associated with a subsequent instruction into said predetermined set of bit positions.

Claim 6

A computer according to any one of claims 1 to 3 in which said processor includes an operand register and a register arranged to hold a value derived from said function bits and to which said control means is responsive to determine the operation of the processor, said function set including a plurality of direct functions in response to which the said control means is arranged to cause the processor to carry out an operation on an operand held in the said operand register.

Claim 7

A computer according to claim 4 in which the said one of the processor registers comprises the said operand register.

Claim 8

A microcomputer comprising a computer according to any one of claims 1 to 5 formed as an integrated circuit device.

Claim 9

A microcomputer comprising an integrated circuit device with memory and a processor providing a plurality of registers, one of which is an operand register, and control means controlling the input and output of data from said memory and said registers, said control means being arranged to cause the processor to execute a number of operations on data held in one of more of the registers in response to a stored program consisting of a plurality of instructions for sequential execution by the processor, each instruction having a set of function bits which designate a required function selected from a function set comprising (a) direct functions in response to which said control means is arranged to cause the processor to carry out a required operation on an operand in the operand register, and (b) one or more other functions in response to which said control means is arranged to vary the location of data within the operand register to permit operands of different lengths.

Claim 10

A microcomputer comprising an integrated circuit device with memory and a processor providing a plurality of registers, one of which is an operand register, and control means controlling the input and output of data from said memory and said registers, said control means being arranged to cause the processor to execute a number of operations on data held in one of more of the registers in response to a stored program consisting of a plurality of instructions for sequential execution by the processor, each instruction having a set of function bits which designate a required function selected from a function set comprising (a) direct functions in response to which said control means is arranged to cause the processor to carry out a required operation on an operand in the operand register, and (b) one or more other functions in response to which said control means is arranged to vary the location of data within the operand register to permit operands of different lengths.

Claim 11

A microcomputer according to claim 7 in which said processor includes means for loading into said operand register data bits corresponding to each instruction and in which said control means is arranged to respond to a said other function which comprises a prefixing function by transferring data in said operand register to positions of different significance to allow addition into the operand register of data associated with more than one instruction, and thereby permit accumulation of operands of different bit length.

Claim 12

. A microcomputer according to claim 7 or 8 in which said function set includes at least one indirect function in response to which said control means causes the processor to use the contents of the operand register to indicate one of a plurality of a possible operations to be effected by the processor on data held in one or more other registers other than the said operand register.

Claim 13

A microcomputer according to claim 6 or claim 7 in which said control means comprises a micro-instruction program arranged to provide a plurality of selectable output signals in the form of micro-instructions which control the processor registers, and address means responsive to the function bits to provide an address signal to the micro-instruction program to select one or more micro-instructions dependent on said address.

Claim 14

A microcomputer according to claims 9 and 10 in which said address means is arranged to use the contents of the operand register to select an address in the micro-instruction program in response to an instruction including an indirect function.

Claim 15

A microcomputer according to claim 9 in which said processor in response to a direct or indirect function is arranged to effect an operation on data held in said memory in addition to data held in a process register.

Claim 16

A microcomputer according to claim 6 or claim 7 in which the function set includes two prefixing functions, a first prefixing function permitting variable length positive values and a second prefixing function allowing variable length negative values.

Claim 17

A microcomputer according to claim 6 or claim 7 having a word length equal to the bit length of said operand register and the data associated with each instruction has a number of bits less than the word length of the microcomputer.

Claim 18

A microcomputer according to claim 14 in which each instruction is one byte long and the processor registers have a bit length which is an integral number of bytes.

Claim 19

A microcomputer according to claim 15 wherein the word length of the microcomputer is an integral multiple of bytes and the function of each instruction is represented by four bits.

Claim 20

A microcomputer according to claim 7 further comprising a plurality of communication channels for permitting transmission of messages to and from a process executed by the microcomputer, said communication channels, processor and memory being provided on a single silicon chip.

Claim 21

A microcomputer according to claim 7 in which the processor includes an operand register and a plurality of other registers arranged in a stack whereby when data is written into or read from one register in the stack, data is moved up or down in the other registers in the stack.