Microcomputer

Claim 2

A microcomputer comprising an integrated circuit device having a processor and memory in the form of RAM on the same integrated circuit device, and a plurality of communication links each including a register for storing a plurality of data bits and each arranged to provide a communication path for sole connection to a similar link of a further microcomputer whereby each microcomputer forms a building block for a network of microcomputers.

Claim 3

A network of interconnected microcomputers each comprising a processor and memory in the form of RAM on a single integrated circuit device, each microcomputer having a plurality of communication links each interconnected by connecting means it with another microcomputer in the network, said links each forming part of a point to point connection which solely interconnects a respective pair of microcomputers and is not shared with any other microcomputer or memory, said links each including at least one register for holding a plurality of bits of data to be transmitted or received through the link.

Claim 4

A network of interconnected microcomputers each comprising a processor and memory in the form of RAM on a single integrated circuit device, each microcomputer having a plurality of communication links each interconnected by connecting means it with another microcomputer in the network, said links each forming part of a point to point connection which solely interconnects a respective pair of microcomputers and is not shared with any other microcomputer or memory, said links each including at least one register for holding a plurality of bits of data to be transmitted or received through the link.

Claim 5

A microcomputer including on the same integrated circuit device memory in the form of RAM and a processor, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a required function to be executed by the processor, the function being one of a set of selectable functions, wherein: (a) the microcomputer includes a plurality of communication links each arranged to provide a communication path for sole connection to a corresponding link of a further microcomputer, said communication links each including a register for storing a plurality of data bits for transmission through the communication link and temporary store means for receiving pointer values indicating the state of the link for use in synchronising message transmission through the link, and (b) said processor includes: (i) a plurality of registers and data transfer means for use in data transfers to and from said registers, (ii) means for receiving each instruction and loading into one of the registers a value corresponding to the function bits of the instruction, and (iii) control means for controlling said data transfer means and registers and arranged to respond to said function bits to cause the processor to operate in accordance with said function bits, the function set including one or more functions which cause said control means to load into the temporary store of the communication links pointer values for use in synchronising message transmission through the communication links.

Claim 6

A microcomputer including on the same integrated circuit device memory in the form of RAM and a processor, said processor being arranged to execute a number of operations on data in response to a program consisting of a plurality of instructions for sequential execution by the processor, each instruction including a set of function bits which designate a required function to be executed by the processor, the function being one of a set of selectable functions, wherein: (a) the microcomputer includes a plurality of communication links each arranged to provide a communication path for sole connection to a corresponding link of a further microcomputer, said communication links each including a register for storing a plurality of data bits for transmission through the communication link and temporary store means for receiving pointer values indicating the state of the link for use in synchronising message transmission through the link, and (b) said processor includes: (i) a plurality of registers and data transfer means for use in data transfers to and from said registers, (ii) means for receiving each instruction and loading into one of the registers a value corresponding to the function bits of the instruction, and (iii) control means for controlling said data transfer means and registers and arranged to respond to said function bits to cause the processor to operate in accordance with said function bits, the function set including one or more functions which cause said control means to load into the temporary store of the communication links pointer values for use in synchronising message transmission through the communication links.

Claim 7

A microcomputer according to claim 3 in which each link provides two unidirectional channels, one for outputs and one for inputs, each channel having a register for storing data bits and temporary store means for receiving pointer values.

Claim 8

A microcomputer according to claim 4 in which each communication link includes control logic arranged to cause transmission of data from a said register in an output channel of a communication link and to detect receipt of data in a said register of an input channel of a link, whereby communication between microcomputers may be effected concurrently through a plurality of links.

Claim 9

A microcomputer according to claims 4 and 5 in which said control logic is arranged to permit concurrent communication via the output and input channels of any one link.

Claim 10

A microcomputer according to claim 5 or claim 6 in which the control logic is arranged to permit data transfers between the registers of a pair of links independently of the processor, thereby permitting message transmission concurrently with process execution by the processor.

Claim 11

A microcomputer according to any of claims 5 to 7 in which said control logic includes means responsive to said pointer values in the temporary store means of each link and means for loading a pointer value into the said temporary store means for use in synchronising message transmission.

Claim 12

A microcomputer according to claim 8 in which said control logic includes means for generating signals for supply to the processor to indicate the state of the link.

Claim 13

A microcomputer according to claims 4 and 5 in which said control logic is arranged to respond to the state of registers in both input and output channels of each link and to cause transmission from an output channel of a data string and includes means for generating and detecting special values indicating-the beginning and end of the string and means to cause an output channel to transmit an acknowledgment signal when the input channel of the same link has received the said special value representing the end of a data string.

Claim 14

A microcomputer according to any of claims 4 to 10 wherein the memory of the microcomputer provides one or more communication channels for message transmission between processes executed on the same microcomputer, each channel having at least one word location arranged to receive a pointer value for use in synchronising message transmission between the said processes, the said control means being arranged to respond to a selected function from the function set to locate a pointer value in said word location indicating the state of the channel for use in synchronising message transmission.

Claim 15

1 2. A microcomputer according to claim 11 in which the processor is arranged to use the same function, selected from the function set, for message synchronisation between processes on the same microcomputer as for processes on different microcomputers.

Claim 16

A microcomputer according to claims 4 to 12 in which said processor includes means for providing pointer values each indicating a respective process which is executed by the microcomputer, said control means being arranged to respond to functions in the function set to load into said register of the communication link a pointer indicating a particular process that is waiting to communicate through said channel together with means for loading into said register a special pointer value to indicate that no process is waiting to communicate through that channel.

Claim 17

A network of interconnected microcomputers, each microcomputer being in accordance with claim 3 or claim 4 and each microcomputer being connected to another microcomputer by connecting means between respective communication links, each connecting means between two microcomputers comprising two unidirectional point to point connections providing respectively input and output paths for each microcomputer.

Claim 18

A network according to claim 14 in which each link is arranged to transmit a message as a serial string of bits and the said point to point connections provide a message path which is one bit wide.

Claim 21

A method according to claim 16 in which a link of a microcomputer in said array is operated to transmit an output message through an output connection of a link concurrently with receipt of an input message through an input connection of the link.

Claim 22

A method according to claim 16 or claim 17 in which control logic of each link is operated to transmit data through a link as a serial string of data bits and generates a first distinguishing bit pattern at the beginning of each message and a second different distinguishing bit pattern at the end of each message whereby the control logic of a receiving link may detect the beginning and end of each message.

Claim 23

A method according to claim 18 in which the control logic of a receiving link is arranged to generate an acknowledgement bit pattern for transmission to a transmitting link to indicate receipt of data of a predetermined bit length.