Output multiplexer having one gate delay

Claim 2

A multiplexer (10) having a plurality of input conductors (52, 54, 56, 58) each responsive to an input having a first and second state and a plurality of select conductors (24, 26) each responsive to a select signal, for providing an output, comprising: a select circuit (12) comprising a plurality of gates 16, 18, 20, 22), each of said input conductors coupled to at least two of said gates, each of said gates having a first gate output having a first and second state and a second gate output having a first and second state, each of said gates comprising differentially coupled transistors, each of said transistors having a collector, each of said collectors providing one of said first and second gate outputs, said collectors dotted so as to provide a plurality of select outputs; and a multiplexer gate (14) coupled to said plurality of input conductors and said select circuit and responsive to said select outputs for determining said output.

Claim 3

A multiplexer having four input conductors (52, 54, 56, 58), each responsive to an input, and two select conductors (24, 26), each responsive to a select signal, for providing an output, comprising: a select circuit (12) comprising: a first gate (16) coupled to a first of said select conductors (24) for providing a first gate signal and a first gate bar signal; a second gate (20) coupled to said first of said select conductors for providing a second gate signal and a second gate bar signal; a third gate (18) coupled to a second of said select conductors (26) for providing a third gate signal and a third gate bar signal; and a fourth gate (22) coupled to said second of said select conductors for providing a fourth gate signal and a fourth gate bar signal, said fourth gate signal being combined with said third gate signal to provide a first select output, said first gate bar signal being combined with said third gate bar signal to provide a second select output, said second gate signal being combined with said fourth gate signal to provide a third select output, said second gate bar signal being combined with said fourth gate bar signal to provide a fourth select output; and a multiplexer gate (14) coupled to said four input conductors and said select circuit and responsive to said first through fourth select outputs for providing said output, said output having a first and second state.

Claim 4

A multiplexer having four input conductors (52, 54, 56, 58), each responsive to an input, and two select conductors (24, 26), each responsive to a select signal, for providing an output, comprising: a select circuit (12) comprising: a first gate (16) coupled to a first of said select conductors (24) for providing a first gate signal and a first gate bar signal; a second gate (20) coupled to said first of said select conductors for providing a second gate signal and a second gate bar signal; a third gate (18) coupled to a second of said select conductors (26) for providing a third gate signal and a third gate bar signal; and a fourth gate (22) coupled to said second of said select conductors for providing a fourth gate signal and a fourth gate bar signal, said fourth gate signal being combined with said third gate signal to provide a first select output, said first gate bar signal being combined with said third gate bar signal to provide a second select output, said second gate signal being combined with said fourth gate signal to provide a third select output, said second gate bar signal being combined with said fourth gate bar signal to provide a fourth select output; and a multiplexer gate (14) coupled to said four input conductors and said select circuit and responsive to said first through fourth select outputs for providing said output, said output having a first and second state.

Claim 5

The multiplexer according to claim 2 wherein said first, second, third, and fourth gates each comprise a first and second differentially connected transistor, a collector of said first transistor of said first gate being coupled to a collector of said first transistor of said second gate, a collector of said second transistor of said first gate being coupled to a collector of said second transistor of said second gate, a collector of said first transistor of said third gate being coupled to a collector of said first transistor of said fourth gate, a collector of said second transistor of said third gate being coupled to a collector of said second transistor of said fourth gate.

Claim 6

The multiplexer according to claim 2 wherein said multiplexer gate comprises: a fifth gate (44) coupled to said first gate and a first of said four input conductors; a sixth gate (46) coupled to. said second gate and a second of said four input conductors; a seventh gate (48) coupled to said third gate and a third of said four input conductors; an eighth gate (50) coupled to said fourth gate and a fourth of said four input conductors; and a ninth gate (60) coupled to said fifth, sixth, seventh, and eighth gate for providing said output.

Claim 7

The multiplexer according to claim 4 further comprising an enabling circuit (64) responsive to an enable signal, said enabling circuit diverting current from said multiplexer gate when enabled.