EP0111085A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Ion implantation process for compound semiconductor
Assignee: International Business Machines Corp
•
Filing: 1983-10-05
•
Granted: —
•
Expires: 2003-10-05
Abstract
Abstract Implanted impurity ions are activated in a compound semiconductor crystal wafer (1, 3), such as GaAs over a broad integrated circuit device area (4) by providing a uniform solid layer (5) (eg 10 ANGSTROM to 500 ANGSTROM thick) of the most volatile element of the compound over the surface (2) of the device area (4) and annealing the crystal wafer at a temperature of 800 DEG C to 900 DEG C for a period of 1 to 20 seconds. <??>The layer (5) of the most volatile element may either be formed on a backing substrate (6) or formed as a coating on the surface (2) of the crystal wafer (1, 3).
Inventors
- 👤 Rodney Trevor Hodgson
- 👤 Thomas Nelson Jackson
- 👤 Hans Stephan Rupprecht
- 👤 Jerry Macpherson Woodall
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:45
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10P14/00; H10P14/60; H10P30/202; H10P30/206; H10P30/28; H10P95/00; H10P95/90; H10P95/904
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
64 words
A process comprising implanting ions in a region of a compound semiconductor crystal wafer and subsequently annealing the wafer, characterised in that a uniform layer of the most volatile element of the compound semiconductor is provided in solid form in contact with said region and the wafer is annealed at a temperature of 800 to 900°C for a period of 1 to 20 seconds.
Claim 2
Dependent Claim
64 words
A process comprising implanting ions in a region of a compound semiconductor crystal wafer and subsequently annealing the wafer, characterised in that a uniform layer of the most volatile element of the compound semiconductor is provided in solid form in contact with said region and the wafer is annealed at a temperature of 800 to 900°C for a period of 1 to 20 seconds.
Claim 3
Dependent Claim
37 words
A process as claimed in claim 1, in which said uniform layer of the most volatile element comprises a layer of that element formed on the surface of the wafer, the ions being implanted through said layer.
Claim 4
Dependent Claim
26 words
A process as claimed in claim 2, in which a backing wafer is provided over the layer of the most volatile element during the annealing operation.
Claim 5
Dependent Claim
28 words
A process as claimed in claim 1, in which said uniform layer of the most volatile element comprises a layer of that element formed on a backing substrate.
Claim 6
Dependent Claim
22 words
A process as claimed in claim 4, in which the backing substrate is of similar semiconductor material to that of the wafer.
Claim 7
Dependent Claim
19 words
A process as claimed in any preceding claim, in which the compound semiconductor consists of GaAs, InP or GaAlAs.
Claim 8
Dependent Claim
25 words
A process as claimed in any preceding claim, in which the implanted ions are Si ions implanted to a depth of 100A to 2000 A.
Claim 9
Dependent Claim
23 words
A process as claimed in any preceding claim, in which said uniform layer of the most volatile element is 10A to 500A thick.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.