EP0110313A2
Expired / Lapsed
EP
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Semiconductor integrated circuit device and a method for manufacturing the same
Assignee: Hitachi Ltd
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Filing: 1983-11-23
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Granted: —
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Expires: 2003-11-23
Abstract
Abstract A semiconductor integrated circuit device and a manufacturing method thereof, which device comprises: a semiconductor layer (10) of a predetermined conductivity type formed on a semiconductor substrate (1) of a first conductivity type; a first well region (50) of a second conductivity type formed at a predetermined position at a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region (5) of the first conductivity type formed in contact with said first well region at the surface of said semiconductor layer and to surround said first well region, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region (2) of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region (40) of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; and semiconductor elements (62, 70, 61) formed in said first well region and said second well region.
Inventors
- 👤 Atsuo Watanabe
- 👤 Takahide Ikeda
- 👤 Kiyoshi Tsukuda
- 👤 Mitsuru Hirao
- 👤 Touji Mukai
- 👤 Tatsuya Kamei
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 20:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D84/00; H10D84/90; H10D84/996; H10D48/00; H10D48/30; H10D48/32; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
229 words
A semiconductor integrated circuit device comprising: a semiconductor layer (10) of a predetermined conductivity type formed on a semiconductor substrate (1) of a first conductivity type; a first well region (50) of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region (5) of the first conductivity type formed in contact with said first well region at the surface of said semiconductor layer and to surround said first well region, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region (2) of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region (40) of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; and semiconductor elements (62, 70, 61) formed in said first well region and said second well region.
Claim 2
Dependent Claim
229 words
A semiconductor integrated circuit device comprising: a semiconductor layer (10) of a predetermined conductivity type formed on a semiconductor substrate (1) of a first conductivity type; a first well region (50) of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region (5) of the first conductivity type formed in contact with said first well region at the surface of said semiconductor layer and to surround said first well region, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region (2) of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region (40) of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; and semiconductor elements (62, 70, 61) formed in said first well region and said second well region.
Claim 3
Dependent Claim
55 words
A semiconductor integrated circuit device according to Claim 1 wherein the semiconductor element formed in said first well region is a vertical bipolar transistor (70) and/or a MOS transistor (62) of the first conductivity type, and the semiconductor element formed in said second well region is a MOS transistor (61) of the second conductivity type.
Claim 4
Dependent Claim
27 words
A semiconductor integrated circuit device according to Claim 1 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.
Claim 5
Dependent Claim
29 words
A semiconductor integrated circuit device according to Claim 1 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.
Claim 6
Dependent Claim
240 words
A semiconductor integrated circuit device comprising: a semiconductor layer (10) of a predetermined conductivity type formed on a semiconductor substrate (11) of a first conductivity type; a first well region (50) of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region (5) of the first conductivity type formed at different position from that of said first well region at the surface of said semiconductor layer, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region (2) of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region (40) of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; and semiconductor elements (62, 70, 61) formed in said first well region and said second well region.
Claim 7
Dependent Claim
240 words
A semiconductor integrated circuit device comprising: a semiconductor layer (10) of a predetermined conductivity type formed on a semiconductor substrate (11) of a first conductivity type; a first well region (50) of a second conductivity type formed at a predetermined position of a surface of said semiconductor layer, an impurity concentration of said first well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a second well region (5) of the first conductivity type formed at different position from that of said first well region at the surface of said semiconductor layer, an impurity concentration of said second well region gradually decreasing as it goes from the surface of said semiconductor layer toward said semiconductor substrate; a first buried region (2) of the second conductivity type formed between and adjacent to said first well region and said semiconductor substrate, said first buried region having a higher impurity concentration than an adjacent area of the adjacent first well region; a second buried region (40) of the first conductivity type formed between and adjacent to said second well region and said semiconductor substrate and in substantial contact with said first buried region to surround said first buried region, said second buried region having a higher impurity concentration than an adjacent area of the adjacent second well region; and semiconductor elements (62, 70, 61) formed in said first well region and said second well region.
Claim 8
Dependent Claim
55 words
A semiconductor integrated circuit device according to Claim 5 wherein the semiconductor element formed in said first well region is a vertical bipolar transistor (70) and/or a MOS transistor (62) of the first conductivity type, and the semiconductor element formed in said second well region is a MOS transistor (61) of the second conductivity type.
Claim 9
Dependent Claim
27 words
A semiconductor integrated circuit device according to Claim 5 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer of the second conductivity type.
Claim 10
Dependent Claim
29 words
A semiconductor integrated circuit device according to Claim 5 wherein said semiconductor layer of said predetermined conductivity type is a semiconductor layer having a substantially uniform impurity concentration distribution.
Claim 11
Dependent Claim
42 words
A semiconductor integrated circuit device according to Claim 5 wherein a boundary plane of said first well region and said second well region and a boundary plane of said first buried region and said second buried region are in substantially same plane.
Claim 12
Independent Claim
177 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first buried region (2).of a second conductivity type at a predetermined position on a surface of a semiconductor substrate (1) of a first conductivity type; (b) forming a second buried region (40) of the first conductivity type in substantial contact with said first buried region on the surface of said semiconductor substrate to surround said first buried region; (c) forming a semiconductor layer (10) of a predetermined conductivity type on said semiconductor substrate; (d) forming a first well region (50) of the second conductivity type at a position corresponding to said first buried region at the surface of said semiconductor layer; (e) forming a second well region (5) of the first conductivity type at a position corresponding to said second buried region at the surface of said semiconductor layer, in contact with said first well region and to surround said first well region; and (f) forming semiconductor elements (62, 70, 61) in said first well region and said second well region.
Claim 13
Independent Claim
177 words
A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first buried region (2).of a second conductivity type at a predetermined position on a surface of a semiconductor substrate (1) of a first conductivity type; (b) forming a second buried region (40) of the first conductivity type in substantial contact with said first buried region on the surface of said semiconductor substrate to surround said first buried region; (c) forming a semiconductor layer (10) of a predetermined conductivity type on said semiconductor substrate; (d) forming a first well region (50) of the second conductivity type at a position corresponding to said first buried region at the surface of said semiconductor layer; (e) forming a second well region (5) of the first conductivity type at a position corresponding to said second buried region at the surface of said semiconductor layer, in contact with said first well region and to surround said first well region; and (f) forming semiconductor elements (62, 70, 61) in said first well region and said second well region.
References Cited (Backward Citations)
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