EP0109853A2
Expired / Lapsed
EP
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Semiconductor memory devices and methods for making the same
Assignee: American Microsystems Holding Corp
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Filing: 1983-11-21
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Granted: —
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Expires: 2003-11-21
Abstract
Abstract An array of MOS transistors (30) formed in a semiconductor substrate having a plurality of continuous diffused lines (bit lines) (7-3, 7-4, 7-5 and 7-6) serving as the source and drain regions of a plurality of MOS transistors. A plurality of conductive word lines (33, 133) are formed over the plurality of diffused lines, crossing the diffused lines at substantially right angles, with each conductive word line serving as the gates of a plurality of MOS transistors. Each transistor of the memory array is formed in a region containing two continuous diffused lines and a single word line. A single electrical contact (36-3, 4, 5, 6) to a bit line is formed for each such diffused line.
Inventors
- 👤 Tarsaim Lal Batra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:17
CPC Classifications
H; H10; H10B; H10B20/00; H10B69/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
175 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type: a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; and a plurality of conductive lines, each conductive line being located above and insulated from an associated one of the channel regions by an insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells. ,
Claim 2
Dependent Claim
175 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type: a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; and a plurality of conductive lines, each conductive line being located above and insulated from an associated one of the channel regions by an insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells. ,
Claim 3
Dependent Claim
197 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a plurality of floating gates each located above and insulated from an associated channel region by a first insulation layer; and a plurality of conductive lines each located above and insulated from an associated one of the floating gates by a second insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the control gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells.
Claim 4
Dependent Claim
197 words
A semiconductor memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a first doped region of a second conductivity type opposite the first conductivity type; a second doped region of the second conductivity type; a plurality of channel regions located between the first and second doped regions; a plurality of floating gates each located above and insulated from an associated channel region by a first insulation layer; and a plurality of conductive lines each located above and insulated from an associated one of the floating gates by a second insulation layer; the first doped region serving as the source of each cell, the second doped region serving as the drain of each cell, each conductive line serving as the control gate of one of the plurality of cells, and the portion of the substrate between the first and second doped regions and beneath each conductive line serving as the channel of one of the plurality of cells.
Claim 5
Dependent Claim
64 words
A semiconductor memory device as claimed in claim 1 or 2 having a first electrical contact formed within the first doped region and a second electrical contact formed within the second doped region, thereby allowing electrical connection to the first doped region which serves as the source of each cell and to the second doped region which serves as the drain of each cell.
Claim 6
Dependent Claim
46 words
A semiconductor memory device as claimed in claim 1, 2 or 3 comprising additional transistors each having a source, a drain, a gate and a channel, the sources and drains of the additional transistors not being formed as part of the first and second doped regions.
Claim 7
Dependent Claim
207 words
A semiconductor memory device having a plurality of R x S cells, each said cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substate of a first conductivity type; a core region within the substrate and within which the plurality of cells are formed; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; and a first insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel.
Claim 8
Dependent Claim
207 words
A semiconductor memory device having a plurality of R x S cells, each said cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substate of a first conductivity type; a core region within the substrate and within which the plurality of cells are formed; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; and a first insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel.
Claim 9
Dependent Claim
263 words
A semiconductor memory device having a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate and within which the plurality of cells are formed; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; a plurality of R x S floating gates, each floating gate being unequally associated with one of the R x S portions of the S conductive lines lying between the R+l doped regions, and each floating gate being insulated from the substrate, the plurality of doped regions and the plurality of conductive lines; and a first insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel.
Claim 10
Dependent Claim
263 words
A semiconductor memory device having a plurality of R x S cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the device comprising: a semiconductor substrate of a first conductivity type; a core region within the substrate and within which the plurality of cells are formed; a field region surrounding the core region; a field oxide layer formed on the substrate in the field region; a plurality of R+l doped regions of a second conductivity type opposite the first conductivity type formed within the core region; a plurality of S conductive lines each crossing each of the plurality of doped regions; a plurality of R x S floating gates, each floating gate being unequally associated with one of the R x S portions of the S conductive lines lying between the R+l doped regions, and each floating gate being insulated from the substrate, the plurality of doped regions and the plurality of conductive lines; and a first insulation layer formed between the plurality of doped regions and the plurality of conductive lines, thereby providing electrical insulation therebetween; each cell being formed by one of the plurality of doped regions serving as a source, an associated one of the plurality of doped regions serving as a drain, an associated one of the plurality of conductive lines serving as a gate, and that portion of the substrate located between the source and the drain and beneath the gate serving as the channel.
Claim 11
Dependent Claim
44 words
A semiconductor memory device as claimed in claim 5 or 6 comprising additional transistors each having a source, a drain, a gate and a channel, the sources and drains of the additional transistors being formed as part of the plurality of R+l doped regions.
Claim 12
Dependent Claim
29 words
A semiconductor memory device as claimed in any preceding claim wherein each cell is surrounded by a field region, the field region being covered by a thick field oxide.
Claim 13
Independent Claim
165 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, said method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming said source of each of the MOS transistors, the second doped region forming the drain of each of the MOS transistors, and the portion of the substrate beneath each the gate region serving as the channel of its associated MOS transistor.
Claim 14
Independent Claim
165 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, said method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming said source of each of the MOS transistors, the second doped region forming the drain of each of the MOS transistors, and the portion of the substrate beneath each the gate region serving as the channel of its associated MOS transistor.
Claim 15
Independent Claim
219 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising a MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from the field oxide; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; -forming a relatively thin insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistors, the second doped region forming the drain of each of the MOS transistors, and the portion of the substrate beneath each gate region serving as the channel of its associated MOS transistor.
Claim 16
Independent Claim
219 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising a MOS transistor having a source, a drain, a gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate, thereby leaving selected portions of the substrate free from the field oxide; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; -forming a relatively thin insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistors, the second doped region forming the drain of each of the MOS transistors, and the portion of the substrate beneath each gate region serving as the channel of its associated MOS transistor.
Claim 17
Independent Claim
167 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each said gate region serving as the channel of its associated MOS transistor.
Claim 18
Independent Claim
167 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising an MOS transistor having a source, a drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming in the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thin insulation layer over selected portions of the first and second doped regions and over that portion of the substrate located between the first and second doped regions; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistor, the second doped region forms the drain of each MOS transistor, and the portion of the substrate beneath each said gate region serving as the channel of its associated MOS transistor.
Claim 19
Independent Claim
235 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising a MOS transistor having a source, a - drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate leaving selected portions of the substrate free from the field oxide; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming a relatively thin first insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; forming a plurality floating gate regions on the first insulation layer; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistors, said second doped region forms said drain of each said MOS transistor, and said portion of said substrate beneath each said gate region serves as the channel of its associated MOS transistor.
Claim 20
Independent Claim
235 words
A method of forming in a semiconductor substrate of a first conductivity type an integrated circuit memory device having a plurality of cells, each cell comprising a MOS transistor having a source, a - drain, a control gate, a floating gate, and a channel, and each cell being capable of storing a single binary digit, the method comprising the steps of: forming a patterned field oxide layer on the surface of the substrate leaving selected portions of the substrate free from the field oxide; forming in the selected portions of the substrate first and second doped regions of a second conductivity type opposite the first conductivity type; forming a relatively thick insulation layer over a substantial portion of the first and second doped regions; forming a relatively thin first insulation layer over those portions of the first and second doped regions which are not covered by the relatively thick insulation layer and over that portion of the substrate located between the first and second doped regions; forming a plurality floating gate regions on the first insulation layer; and forming a plurality conductive gate regions on the relatively thin insulation layer; the first doped region forming the source of each of the MOS transistors, said second doped region forms said drain of each said MOS transistor, and said portion of said substrate beneath each said gate region serves as the channel of its associated MOS transistor.
References Cited (Backward Citations)
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