EP0109602A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Fault tolerable redundancy control
Assignee: Hitachi Ltd
•
Filing: 1983-11-07
•
Granted: —
•
Expires: 2003-11-07
Abstract
Abstract A redundant control system in which three output signals (101A, 101B, 101C) from three equivalent signal processors (1A, 1B, 1C) are compared with each other to judge whether each of the output signals is normal or abnormal, an abnormal output signal thus determined is replaced by a set signal (103) having a predetermined level, and then a majority operation is performed for normal output signals and the set signal to obtain a control signal (602). The control signal (602) is formed of the logical product or logical sum of two normal output signals according as the predetermined level of the set signal (103) is "1" or "0". In the case where a circuit for generating the above-mentioned control signal (602) are formed in triplicate and a majority operation is performed for three control signals (602A, 6028, 602C), a fault occurring at other circuit portions than a majority logic circuit (92) at the final stage is permissible. Further, the reliability of the control system is enhanced by forming abnormality detecting means (63) in triplicate and performing a majority operation for the outputs of three abnormality detecting means (63A, 63B, 63C).
Inventors
- 👤 Kazuhiko Ishii
- 👤 Atomi Noguchi
- 👤 Yoshimi Gotoh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 10:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/18; G06F11/183; G06F11/184; G05; G05B; G05B9/00; G05B9/02; G05B9/03; H; H04; H04L; H04L1/00; H04L1/22; G06F11/185
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
162 words
A redundant control system in which a plurality of equivalent control signals (101A, 101B, 101C) from a plurality of equivalent signal processors (lA, 1B, 1C) are subjected to majority logic operation, to deliver a system control signal (602), said redundant control system comprising: an error detecting circuit (63) applied with said control signals (101A, 101B, 101C) for comparing said control signals with each other to check the presence of a control signal different in level from that of the majority of the control signals and to generate an error detection signal (603A, 603B, 603C) on an output line corresponding to said different control signal; a switching circuit (61) applied with said control signals, said error detection signal and a set signal (103) for replacing said control signal indicated by said error detection signal with said set signal; and a majority logic circuit (62) applied with outputs. of said switching circuit for performing a majority logic operation to generate an output signal (602).
Claim 2
Dependent Claim
162 words
A redundant control system in which a plurality of equivalent control signals (101A, 101B, 101C) from a plurality of equivalent signal processors (lA, 1B, 1C) are subjected to majority logic operation, to deliver a system control signal (602), said redundant control system comprising: an error detecting circuit (63) applied with said control signals (101A, 101B, 101C) for comparing said control signals with each other to check the presence of a control signal different in level from that of the majority of the control signals and to generate an error detection signal (603A, 603B, 603C) on an output line corresponding to said different control signal; a switching circuit (61) applied with said control signals, said error detection signal and a set signal (103) for replacing said control signal indicated by said error detection signal with said set signal; and a majority logic circuit (62) applied with outputs. of said switching circuit for performing a majority logic operation to generate an output signal (602).
Claim 3
Dependent Claim
44 words
A redundant control system according to Claim 1, further comprising a latch circuit (64) for latching the output of said error detecting circuit (63), and a masking circuit (68) for preventing said latch circuit from generating an output signal, during a predetermined time period.
Claim 4
Dependent Claim
87 words
A redundant control system according to Claim 1, further comprising a diagnosing circuit (65) applied with the outputs of said switching circuit (61) and the output of said majority logic circuit (62) for performing a majority logic operation for the outputs of said switching circuit and comparing the result of said majority logic operation with the output of said majority logic circuit, to deliver a logic fault signal (F) when the result of said majority logic operation is different from the output of said majority logic circuit.
Claim 5
Dependent Claim
122 words
A redundant control system according to Claim 1, wherein said switching circuit (61) includes NOR means (611A, 611B, 611C) applied with said control signals (101A, 101B, 101C) and the error detection signal (102A, 102B, 102C) to perform NOR logic operation of each of the control signals and a corresponding one of the detection signal, AND means (612A, 614A, 612B, 614B, 612C, 614C) applied with said error detection signal and said set signal (103) to perform AND logic operation of each one of the detection signal and the set signal, and NOR means (616A, 616B, 616C) applied with the output of each one of said NOR means and the output of a corresponding one of said AND means to perform NOR logic operation.
Claim 6
Dependent Claim
29 words
A redundant control system according to Claim 4, wherein said AND means includes a series combination of an NAND gate (612A, 612B, 612C) and an inverter (614A, 614B, 614C).
Claim 7
Dependent Claim
23 words
A redundant control system according to Claim 1, wherein said error detection signal is applied to said switching circuit through said signal processor.
Claim 8
Dependent Claim
30 words
A redundant control system according to Claim 1, further comprising display means (3) for displaying the presence of an accident in accordance with the output of said error detecting circuit.
Claim 9
Dependent Claim
52 words
A redundant control system according to Claim 1, further comprising equivalent sensors (82) of the same function each supplying an output thereof to a corresponding one of said signal processors (lA, 1B, 1C) to cause said signal processors to deliver said control signals on the basis of the outputs of said sensors.
Claim 10
Dependent Claim
195 words
A redundant control system in which three ON-OFF control signals from three equivalent processors (lA, 1B, 1C) are subjected to a majority logic operation to deliver a majority control signal (600), said redundant control system comprising: three switching circuits (61A, 61B, 61C), each of said switching circuits being applied with said control signals (101A, 101B, lOlC), three changeover signals (102A, 102B, 102C) and a set signal (103) for generating three output signals, each being equal to a corresponding one of said control signals when a corresponding one of said changeover signals is in the OFF-state and for converting said output signal into a signal determined by the ON or OFF state of said set signal when said corresponding changeover signal is in the ON-state; three first majority logic circuits (62A, 62B, 62C) corresponding to said switching circuits (61A, 61B, 61C), each of said first majority logic circuits being applied with three outputs from a corresponding one of said switching circuits, to perform a majority logic operation; and a second majority logic circuit (92) applied with three outputs from said first majority logic circuits for performing a majority operation to deliver said majority control signal (600).
Claim 11
Dependent Claim
195 words
A redundant control system in which three ON-OFF control signals from three equivalent processors (lA, 1B, 1C) are subjected to a majority logic operation to deliver a majority control signal (600), said redundant control system comprising: three switching circuits (61A, 61B, 61C), each of said switching circuits being applied with said control signals (101A, 101B, lOlC), three changeover signals (102A, 102B, 102C) and a set signal (103) for generating three output signals, each being equal to a corresponding one of said control signals when a corresponding one of said changeover signals is in the OFF-state and for converting said output signal into a signal determined by the ON or OFF state of said set signal when said corresponding changeover signal is in the ON-state; three first majority logic circuits (62A, 62B, 62C) corresponding to said switching circuits (61A, 61B, 61C), each of said first majority logic circuits being applied with three outputs from a corresponding one of said switching circuits, to perform a majority logic operation; and a second majority logic circuit (92) applied with three outputs from said first majority logic circuits for performing a majority operation to deliver said majority control signal (600).
Claim 12
Dependent Claim
151 words
A redundant control system according to Claim 9, further comprising three error detecting circuits (63A, 63B, 63C) corresponding to said switching circuits, each of said error detecting circuits being applied with three output signals from a corresponding one of said switching circuits for putting one of said output signals in the ON-state and putting the remaining output signals in the OFF-state when said one output signal is different in level from the remaining output signals, and three third majority logic circuits (94A, 94B, 94C) corresponding to said control signals (101A, 101B, 101C), each of said third majority logic circuits being applied with three output signals delivered from said error detecting circuits (63A, 63B, 63C) and corresponding to one of said control signals (101A, 101B, 101C), for performing a majority operation to detect an error signal from said control signals on the basis of the outputs of said third majority logic circuits.
Claim 13
Dependent Claim
97 words
ll. A redundant control system according to Claim 10, further comprising first latch circuits (64A, 64B, 64C), each of said first latch circuits being connected between one of said error detecting circuits (63A, 63B, 63C) and said third majority logic circuits (94A, 94B, 94C) for preventing output signals of the error detecting circuit from being applied to said third majority logic circuits (94A, 94B, 94C), during a predetermined masking time period, to get rid of a transient error signal from the error detecting circuit due to the asynchronism of three output signals of a corresponding switching circuit.
Claim 14
Dependent Claim
131 words
A redundant control system according to Claim 9, further comprising three diagnosing circuits (65A, 65B, 65C) corresponding to said first majority logic circuits (62A, 62B, 62C), each of said diagnosing circuits being applied with three output signals of a corresponding one of said switching circuits for performing a majority logic operation to diagnose a corresponding one of said first majority logic circuits on the basis of the comparison between the result of said majority logic operation and the output of said corresponding first majority logic circuit, and a fourth majority logic circuit (98) applied with three output signals from said three diagnosing circuits (65A, 65B, 65C) for performing a majority logic operation to diagnose said third majority logic circuits on the basis of the output of said fourth majority logic circuit.
Claim 15
Dependent Claim
94 words
A redundant control system according to Claim 12, further comprising second latch circuits (66A, 66B, 66C), each of said second latch circuits being connected between one of said diagnosing circuits (65A, 65B, 65C) and said fourth majority logic circuit (98) for preventing the output signal of a corresponding one of said diagnosing circuits from being applied to said fourth majority logic circuit (98), during a predetermined masking time period, to get rid of a transient erroneous output from the diagnosing circuit due to the asynchronism of three output signals of a corresponding switching circuit.
References Cited (Backward Citations)
EP0007270A1
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.