EP0109248A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Magnetic recorder write data compensating circuit
Assignee: Fujitsu Ltd
•
Filing: 1983-11-08
•
Granted: —
•
Expires: 2003-11-08
Abstract
Abstract 57 A write data compensating circuit in a magnetic recorder comprises a shifting circuit (40) for shifting binary data (Din) in time relation and for producing front, present, and rear signals related to the binary data, and a combination logic circuit (50) for applying a preshift to the present signal provided as write data in accordance with a pattern of the front, present, and rear signals. The combination logic circuit comprises a first circuit (51-55) which is operative to detect the pitch of each two adjacent inversions of magnetization to be created by the write data, and a second circuit (58-63) operative to adjust each pulse width of the write data on the basis of an analysis by the first circuit.
Inventors
- 👤 Hiroshi Uno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 04:27
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10194; G11B20/10212
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
165 words
A write data compensating circuit in'a magnetic recorder, including a shifting circuit (40) for shifting binary data (Din) in time series in synchronization with a clock (CLK) so as to produce a front signal, a present signal, and a rear signal in dependence upon the binary data; and a combination logic circuit (50) to receive at least the front, present, and rear signals and to apply a preshift to the present signal provided as write data (WD) representing the binary data, characterised in that the combination logic circuit comprises first means (51-55) operative to detect the pitch of each two adjacent inversions of magnetization to be created on a recording medium on which the binary data are recorded in the form of the write data, and second means (59-63) operative to adjust each pulse width of the write data by selectively applying a preshift to the present signal in accordance with the pitch of each two adjacent inversions of magnetization detected by the first means.
Claim 2
Dependent Claim
165 words
A write data compensating circuit in'a magnetic recorder, including a shifting circuit (40) for shifting binary data (Din) in time series in synchronization with a clock (CLK) so as to produce a front signal, a present signal, and a rear signal in dependence upon the binary data; and a combination logic circuit (50) to receive at least the front, present, and rear signals and to apply a preshift to the present signal provided as write data (WD) representing the binary data, characterised in that the combination logic circuit comprises first means (51-55) operative to detect the pitch of each two adjacent inversions of magnetization to be created on a recording medium on which the binary data are recorded in the form of the write data, and second means (59-63) operative to adjust each pulse width of the write data by selectively applying a preshift to the present signal in accordance with the pitch of each two adjacent inversions of magnetization detected by the first means.
Claim 3
Dependent Claim
27 words
A circuit as claimed in Claim 1, characterised in that the first means (51-55) is operative to detect a variety of pitches of the inversions of magnetization.
Claim 4
Dependent Claim
80 words
A circuit as claimed in Claim 2, characterised in that the variety of pitches are classified into at least four modes, namely a first mode in which the present signal is sandwiched between the front and rear signal, a second mode in which the present signal is accompanied by the front signal only, a third mode in which the present signal is accompanied by the rear signal only, and a fourth mode in which no front and rear signals exist.
Claim 5
Dependent Claim
103 words
A circuit as claimed in Claim 3, characterised in that the second means includes a first delay unit (62) having a first delay time and a second delay unit (63) having a second delay time longer than the first delay time; in that the second means is operative to produce, as the write data (WD), the present signal without passing through the delay units in the second mode, by way of the second delay unit in the third mode, by way of the first delay unit in the first mode, and by way of the first delay unit in the fourth mode, respectively.
Claim 6
Dependent Claim
55 words
A circuit as claimed in Claim 3 or Claim 4, characterised in that the second means (59-63) is provided, at its input stage, with registers (59-61) for momentarily storing the present signals provided in the first to fourth modes and for producing each of the thus stored present signals in synchronization with the clock (CLK).
Claim 7
Dependent Claim
67 words
A circuit as claimed in Claim 5, characterised in that each of the registers (59-61) comprises a D flip-flop having a data input terminal to receive a corresponding present signal, a clock input terminal to receive the clock (CLK), an output terminal to produce the stored present signal in synchronization with the clock, and an inverted output terminal to produce the inverse of the output terminal signal.
Claim 8
Dependent Claim
79 words
A circuit as claimed in claim 6, characterised in that each of the delay units comprises a first comparator (64-1, 64-2, 64-3) to receive differential output signals from the corresponding D flip-flop (59-61) at its output and inverted output terminals, and a capacitor (C 1 , C 2 ) is bridged between a respective differential output signal line pair, which capacitor cooperates with resistors CR 3 -R 6 ) arranged in the form of a CR time constant circuit.
Claim 9
Dependent Claim
60 words
A circuit as claimed in Claim 7, characterised in that the first comparator (64-2, 64-3) are further coupled to respective second comparators (64-2', 64-3') via differential output signal line pairs between which a respective compacitor (C 3 ,C 4 ) is bridged and cooperates with resistors (R 9 -B 12 ) so as to form a CR time constant circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.