EP0109069A2
Expired / Lapsed
EP
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Dynamic type semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1983-11-11
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Granted: —
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Expires: 2003-11-11
Abstract
Abstract A dynamic type semiconductor memory device having refreshing function includes a clock pulse generating circuit (22) having a row clock pulse generating section (22-4) which includes a plurality of cascade-connected delay circuits (220-1 to 220-N), a plurality of MOS transistors (TR1) to TR(N-1)) selectively connected between said delay circuits (220-1 to 220-N), and a gate control circuit (221) for changing conduction resistances of the MOS transistors (TR1) to TR(N-1)) according to the level of a refreshing signal.
Inventors
- 👤 Naokazu Miyawaki
- 👤 Mitsugi Ogura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; Y; Y10; Y10S; Y10S257/00; Y10S257/93
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
215 words
A dynamic type semiconductor memory device comprising a memory cell array (2); an address data generating circuit (4); row and column address buffer circuits (6, 8); row and column decoder circuits (10, 12); a control signal generating circuit (20) for generating refreshing and timing control signals; refreshing circuits (24, 26) for performing refreshing operation responsive to the refreshing control signal supplied from said control signal generating circuit (20); and a clock pulse generating circuit (22) for generating clock pulses responsive to the timing control signals supplied from said control signal generating circuit (20) to drive the row and column address buffer circuits (6, 8) and the row and column decoder circuits (10, 12), said clock pulse generating circuit (22) including a clock pulse generating section (22-4) which has a plurality of cascade-connected delay circuits (220-1 to 220-N) and which serves to supply clock pulses to the row address buffer circuit (6) and the row decoder circuit (10); characterized in that said clock pulse generating section (22-4) further includes a plurality of delay elements (TR1 to TR(N-1)) selectively connected to output terminals of the delay circuits (220-1 to 220-N) and whose delay amounts are variable, and a control circuit for controlling delay amounts of the delay elements (TR1 to TR(N-1)) responsive to the refreshing control signal.
Claim 2
Dependent Claim
215 words
A dynamic type semiconductor memory device comprising a memory cell array (2); an address data generating circuit (4); row and column address buffer circuits (6, 8); row and column decoder circuits (10, 12); a control signal generating circuit (20) for generating refreshing and timing control signals; refreshing circuits (24, 26) for performing refreshing operation responsive to the refreshing control signal supplied from said control signal generating circuit (20); and a clock pulse generating circuit (22) for generating clock pulses responsive to the timing control signals supplied from said control signal generating circuit (20) to drive the row and column address buffer circuits (6, 8) and the row and column decoder circuits (10, 12), said clock pulse generating circuit (22) including a clock pulse generating section (22-4) which has a plurality of cascade-connected delay circuits (220-1 to 220-N) and which serves to supply clock pulses to the row address buffer circuit (6) and the row decoder circuit (10); characterized in that said clock pulse generating section (22-4) further includes a plurality of delay elements (TR1 to TR(N-1)) selectively connected to output terminals of the delay circuits (220-1 to 220-N) and whose delay amounts are variable, and a control circuit for controlling delay amounts of the delay elements (TR1 to TR(N-1)) responsive to the refreshing control signal.
Claim 3
Dependent Claim
37 words
A dynamic type semiconductor memory device according to claim 1, characterized in that each of said delay elements is a MOS transistor (TR1 to TR(N-1)) connected between two successive stages of said delay circuits (220-1 to 220-N).
Claim 4
Dependent Claim
73 words
A dynamic type semiconductor memory device according to claim 1, characterized in that each of said delay elements comprise MOS transistors (TR(N+1) to TR(2N-1)), one end of each of their current paths being connected to the output terminal of one of said plural delay circuits (220-1 to 220-N), and capacitive means (Cl to C(N-1)) connected between the other end of each of said MOS transistors (TR(N+1) to TR(2N-1)) and a reference potential terminal.
Claim 5
Dependent Claim
68 words
A clock pulse generating circuit including a plurality of cascade-connected delay circuits characterized by further comprising a plurality of delay elements (TR1 to TR(N-1)) selectively connected to output terminals of said delay circuits (220-1 to 220-N) and whose delay amount is variable, and a control circuit (221) for supplying a control signal to said delay elements (TR1 to TR(N-1)) to change the delay amount of said delay elements.
Claim 6
Dependent Claim
68 words
A clock pulse generating circuit including a plurality of cascade-connected delay circuits characterized by further comprising a plurality of delay elements (TR1 to TR(N-1)) selectively connected to output terminals of said delay circuits (220-1 to 220-N) and whose delay amount is variable, and a control circuit (221) for supplying a control signal to said delay elements (TR1 to TR(N-1)) to change the delay amount of said delay elements.
Claim 7
Dependent Claim
36 words
A clock pulse generating circuit according to claim 4, characterized in that each of said delay elements is a MOS transistor (TR1 to TR(N-1)) connected between two successive stages of said delay circuits (220-1 to 220-N).
Claim 8
Dependent Claim
71 words
A clock pulse generating circuit according to claim 4, characterized in that each of said delay elements comprises a MOS transistor (TR(N+l) to TR(2N-1)) whose current path is connected to the output terminal of a corresponding one of said delay circuits (220-1 to 220-N), and capacitive means (Cl to C(N-1)) connected between the other end of the current path of said MOS transistor (TR(N+1) to TR(2N-1)) and a reference potential terminal.
References Cited (Backward Citations)
No citation records indexed.
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