Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A traffic monitoring arrangement for measuring packet traffic through circuitry interfacing a communication channel with a packet switching network, the invention wherein said circuitry comprises: means for generating a packet present signal during a communication of each of a plurality of packets; means responsive to said signal for calculating a first set of bit signals representing the amount of present time consumed in communicating all of said packets; means for storing a second set of bit signals representing a reference time; and means responsive to subsets of bit signals of said first and second sets of bit signals for generating a report signal indicating excursions of said present time from said reference time.
Claim 2
Dependent Claim
113 words
A traffic monitoring arrangement for measuring packet traffic through circuitry interfacing a communication channel with a packet switching network, the invention wherein said circuitry comprises: means for generating a packet present signal during a communication of each of a plurality of packets; means responsive to said signal for calculating a first set of bit signals representing the amount of present time consumed in communicating all of said packets; means for storing a second set of bit signals representing a reference time; and means responsive to subsets of bit signals of said first and second sets of bit signals for generating a report signal indicating excursions of said present time from said reference time.
Claim 3
Dependent Claim
46 words
The arrangement of claim 1 wherein said subsets of bit signals comprise a first and a second subsets of bit signals and said generating means comprising means for selecting from said first and second sets of bit signals said first and second subsets of bit signals.
Claim 4
Dependent Claim
85 words
The arrangement of claim 2 wherein said generating means further comprises a mask register for storing a set of mask bit signals representing a plurality of predetermined excursions; mask circuit means reponsive to said first and second sets of bit signals and stored mask bit signals of said mask register for logically generating said first and second subsets of bit signals; and comparator circuit responsive to said last mentioned bit signals to generate said report signal upon said subsets of bit signals not being equal.
Claim 5
Dependent Claim
75 words
The arrangement of claim 1 wherein said calculating means comprises accumulator means incremented in responsive to said packet present signal under control rate signals; said interfacing circuitry further comprising timer means for generating a control signal upon a definite period of time elapsing; and said calculating means further comprising a present time register responsive to said control signal for storing most significant bit signals of said accumulator means as said first set of bit signals.
Claim 6
Dependent Claim
46 words
The arrangement of claim 4 wherein said accumulator means is further responsive to said control signal for effecting a division by two of the contents of said accumulator means in preparation for receipt of another packet present signal in the next sequential definite period of time.
Claim 7
Dependent Claim
86 words
The arrangement of claim 4 wherein said timer means comprises a counter circuit decremented in response to said rate signals to calculate the elapse of said definite period of time and means responsive to said counter circuit decrementing to zero for generating said control signal; constant register means for storing signals representing said definite period of time; and means responsive to said control signal for transferring the contents of said constant register means to initialize said counter circuit for calculation of said definite period of time.
Claim 8
Dependent Claim
56 words
The arrangement of claim 1 wherein said calculating means comprises means for calculating said first set of bit signals for a present definite period of time; and said storing means comprising a previous time register for storing said second set of bit signals representing a calculated amount of time for a previous definite period of time.
Claim 9
Dependent Claim
93 words
The arrangement of claim 7 wherein said interfacing circuitry further comprises: timer means responsive to rate signals for generating a control signal upon said present definite period of time elapsing; and a present time register responsive to said control signal for storing most significant bit signals of said accumulator means as said first set of bit signals; and said previous time register comprising means responsive to said control signal and a predetermined one of said rate signals to store the contents of said present time register as said second set of bit signals.
Claim 10
Dependent Claim
97 words
The arrangement of claim 8 wherein said subsets of bit signals comprise a first and second subsets of bit signals and said generating means comprises: a mask register for storing a set of mask bit signals representing a plurality of predetermined excursions; mask circuit means responsive to said first and second sets of bit signals and stored mask bit signals of said mask register for logically generating said first and second subsets of bit signals; and comparator circuit means responsive to said last mentioned bit signals for generating said report signal to indicate said plurality of excursions.