Patent US4933562A successfully refreshed from Google Patents.
EP0107415A2
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A static memory circuit
Assignee: Fujitsu Ltd
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Filing: 1983-09-30
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Granted: —
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Expires: 2003-09-30
Abstract
Abstract @ A static memory circuit comprising memory cells arranged in a matrix of word lines and bit lines, a reset circuit for resetting each pair of bit lines to habe an equivalent potential in responce to a charge of a row address signal, the reset circuit having a constitution to generate a reset signal at a first time a certain time period after a first change of the row address signal and to terminate the reset signal at a second time before a second change, followed by the first change, of the row address signal, whereby data destruciton during reading is prevented.
Inventors
- 👤 Eiji Noguchi
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 22:00
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
165 words
A static memory circuit comprising: a plurality of memory cells arranged in a matrix having columns and rows; a plurality of word lines connected to respective rows of the memory cells; a plurality of pairs of bit lines connected to respective columns of the memory cells; and a reset means for resetting at least one of said pairs of bit lines to have an equivalent potential, in response to a change of an input address signal for selecting one of said word lines; said reset means comprising a first reset signal generating circuit for generating a first reset signal, said first reset signal being generated at a first time a certain time period after a first change of said input address signal and being terminated at a second time before a second change, followed by said first change, of said input address signal, whereby said at least one of said pairs of bit lines are reset before said second change of said input address signal.
Claim 2
Dependent Claim
165 words
A static memory circuit comprising: a plurality of memory cells arranged in a matrix having columns and rows; a plurality of word lines connected to respective rows of the memory cells; a plurality of pairs of bit lines connected to respective columns of the memory cells; and a reset means for resetting at least one of said pairs of bit lines to have an equivalent potential, in response to a change of an input address signal for selecting one of said word lines; said reset means comprising a first reset signal generating circuit for generating a first reset signal, said first reset signal being generated at a first time a certain time period after a first change of said input address signal and being terminated at a second time before a second change, followed by said first change, of said input address signal, whereby said at least one of said pairs of bit lines are reset before said second change of said input address signal.
Claim 3
Dependent Claim
31 words
A static memory circuit as set forth in claim 1, wherein said certain time period is so determined as to be longer than a period necessary for accessing a memory cell.
Claim 4
Dependent Claim
110 words
A static memory circuit as set forth in claim 1, wherein said reset means further comprises an address change detecting circuit for detecting a change in the potential of a row address signal so as to provide an address change detecting signal, said row address signal being a signal for selecting one of said rows, and also comprises a delay circuit adapted to receive said address change detecting signal and provide a delay signal generated at said first time, said first reset signal generating circuit generating said first reset signal in response to said delay signal and terminates said first reset signal in response to said address change detecting signal.
Claim 5
Dependent Claim
53 words
A static memory circuit as set forth in claim 3, wherein said reset means further comprises a bit line resetting transistor having a source and a drain connected between each pair of said bit lines, said first reset signal being adapted to be applied to the gate of said bit line resetting transistor.
Claim 6
Dependent Claim
64 words
A static memory circuit as set forth in claim 4, wherein said reset means further comprises bit line precharging transistors each having a drain and a source connected between an end of one of said bit lines and a high voltage terminal of a power supply, said first reset signal being adapted to be applied to the gates of said bit line precharging transistors.
Claim 7
Dependent Claim
52 words
A static memory circuit as set forth in claim 3, wherein said reset means further comprises a second reset signal generating circuit for generating a second reset signal, said second reset signal being generated in response to a change of said input address signal when said first reset signal is being terminated.
Claim 8
Dependent Claim
65 words
A static memory circuit as set forth in claim 6, wherein said second reset signal generating circuit comprises an inverter for providing an inverted signal inverted from said first reset signal, an AND gate for providing a logical product of said inverted signal and said address change detecting circuit, and a monostable multivibrator adapted to receive said logical product to provide said second reset signal.
Claim 9
Dependent Claim
53 words
A static memory circuit as set forth in claim 7, wherein said reset means further comprises a bit line resetting transistor having a source and a drain connected between each pair of said bit lines, said second reset signal being adapted to be applied to the gate of said bit line resetting transistor.
Claim 10
Dependent Claim
64 words
A static memory circuit as set forth in claim 8, wherein said reset means further comprises bit line precharging transistors each having a drain and a source connected between an end of one of said bit lines and a high voltage terminal of a power supply, said second reset signal being adapted to be applied to the gates of said bit line precharging transistors.
Claim 11
Dependent Claim
45 words
A static memory circuit as set forth in claim 3, wherein said reset means further comprises an AND gate adapted to receive said first reset signal and a write enable signal to provide a logical product thereof, said logical product being a second reset signal.
Claim 12
Dependent Claim
53 words
A static memory circuit as set forth in claim 10, wherein said reset means further comprises a bit line resetting transistor having a source and a drain connected between each part of said bit lines, said second reset signal being adapted to be applied to the gate of said bit line resetting transistor.
Claim 13
Dependent Claim
64 words
A static memory circuit as set forth in claim 11, wherein said reset means further comprises bit line precharging transistors each having a drain and a source connected between an end of one of said bit lines and a high voltage terminal of a power supply, said second reset signal being adapted to be applied to the gates of said bit line precharging transistors.
Claim 14
Dependent Claim
45 words
A static memory circuit as set forth in claim 6, wherein said reset means further comprises an AND gate adapted to receive said second reset signal and a write enable signal to provide a logical product thereof, said logical product being a third reset signal.
Claim 15
Dependent Claim
53 words
A static memory circuit as set forth in claim 13, wherein said reset means further comprises a bit line resetting transistor having a source and a drain connected between each part of said bit lines, said third reset signal being adapted to be applied to the gate of said bit line resetting transistor.
Claim 16
Dependent Claim
64 words
A static memory circuit as set forth in claim 14, wherein said reset means further comprises bit line precharging transistors each having a drain and a source connected between an end of one of said bit lines and a high voltage terminal of a power supply, said third reset signal being adapted to be applied to the gates of said bit line precharging transistors.
References Cited (Backward Citations)
No citation records indexed.
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