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EP0107337A2
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Improvements in or relating to sample-and-hold circuits and methods
Assignee: AT&T Inc
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Filing: 1983-09-20
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Granted: —
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Expires: 2003-09-20
Abstract
Abstract A feedback sample and hold circuit has an amplifier A whose output is connected through a sampling switch (S s ) to the input of a buffer (B). A holding capacitor (C H ) is connected between input of the buffer (B) and ground potential. A correction coupling capacitor (C cc ) and a correction holding capacitor (C CH ) are connected between the input of the buffer (B) and ground. A correction switch S c is connected between the amplifier output (14) and the common node (22) of the correction capacitors (C CC , C CH ). When the sampling switch (S s ) opens for the hold condition, the correction switch (S C ) briefly remains closed to permit the amplifier (A) to correct the hold voltage for switching charge feedthrough error from the sampling switch (S s ) by charging the correction holding capacitor (C CH ). The correction coupling capacitor (C cc ) couples this correction in attenuated form to the holding capacitor (C H ).
Inventors
- 👤 Hans Peter Lie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:25
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
109 words
A sample-and-hold circuit including an amplifier (A), a primary sampling switch (5 5 ) connected in a circuit path between an input for a signal source and an input (15) of a buffer (B), a primary holding capacitor (C H ) connected between the input of the buffer and a reference potential point, and feedback means (S F ) responsive to output of the buffer for providing a feedback signal to an input of the amplifier, and characterized by correction sample-and-hold means (SC, C CH ) connected to the output of the amplifier and responsive to switching feedthrough error generated by the sampling switch for substantially correcting such error.
Claim 2
Dependent Claim
109 words
A sample-and-hold circuit including an amplifier (A), a primary sampling switch (5 5 ) connected in a circuit path between an input for a signal source and an input (15) of a buffer (B), a primary holding capacitor (C H ) connected between the input of the buffer and a reference potential point, and feedback means (S F ) responsive to output of the buffer for providing a feedback signal to an input of the amplifier, and characterized by correction sample-and-hold means (SC, C CH ) connected to the output of the amplifier and responsive to switching feedthrough error generated by the sampling switch for substantially correcting such error.
Claim 3
Dependent Claim
70 words
A circuit as claimed in claim 1 wherein the correction means includes a correction sampling switch (S C ) and a correction holding capacitor (C C H ) connected serially respectively, between the output of the amplifier and a reference potential point, and coupling means (C CC ) connected to a node (22) between the correction sampling switch and the correction holding capacitor and serving to provide a correction signal.
Claim 4
Dependent Claim
40 words
A circuit as claimed in claim 2 wherein the coupling means includes a correction coupling capacitor connected between the input of the buffer and the said node and having a capacitance substantially less than that of the primary holding capacitor.
Claim 5
Dependent Claim
27 words
A circuit as claimed in claim 2 or 3 including a correction zeroing switch (S C2 ) connected between a reference potential point and the said node.
Claim 6
Independent Claim
89 words
A method of sampling and holding a signal in a feedback sample-and-hold circuit wherein an amplifier output (14) is sampled and held by means of a primary feedback sample-and-hold circuit (S S ,C H ) to generate a primary held signal, and characterised in that the amplifier output is sampled and held by means of a secondary feedback sample and hold circuit (S Cl ,C CH ) to generate a correction held signal, and an attenuated form of the correction held signal is combined with the primary held signal.
Claim 7
Independent Claim
89 words
A method of sampling and holding a signal in a feedback sample-and-hold circuit wherein an amplifier output (14) is sampled and held by means of a primary feedback sample-and-hold circuit (S S ,C H ) to generate a primary held signal, and characterised in that the amplifier output is sampled and held by means of a secondary feedback sample and hold circuit (S Cl ,C CH ) to generate a correction held signal, and an attenuated form of the correction held signal is combined with the primary held signal.
Claim 8
Dependent Claim
169 words
A sample-and-hold circuit characterised by first (C H ) ' second (C C ), and third (C CH ) capacitors connected serially between two reference voltage points, the common node (15) of the first and second capacitors forming a signal node and the common node (22) of the second and third capacitors forming a correction node, primary sampling switch means (S ) connected at one side to the signal node for selectively connecting the signal node to an input for a signal voltage source, secondary sampling switch means (S c ) for selectively connecting the correction node to an input for a signal voltage source, and correction feedback means, including an operational amplifier (A) having an input coupled to the signal node and an output coupled to the correction node, adapted to correct the voltage at the correction node in response to a change in the voltage at the signal node, upon disconnection of the signal node from the signal voltage source input by the primary sampling switch means.
Claim 9
Dependent Claim
169 words
A sample-and-hold circuit characterised by first (C H ) ' second (C C ), and third (C CH ) capacitors connected serially between two reference voltage points, the common node (15) of the first and second capacitors forming a signal node and the common node (22) of the second and third capacitors forming a correction node, primary sampling switch means (S ) connected at one side to the signal node for selectively connecting the signal node to an input for a signal voltage source, secondary sampling switch means (S c ) for selectively connecting the correction node to an input for a signal voltage source, and correction feedback means, including an operational amplifier (A) having an input coupled to the signal node and an output coupled to the correction node, adapted to correct the voltage at the correction node in response to a change in the voltage at the signal node, upon disconnection of the signal node from the signal voltage source input by the primary sampling switch means.
Claim 10
Dependent Claim
28 words
A circuit as claimed in claim 6 wherein the correction feedback means includes a buffer (B) having an output (16) connected to an input of the operational amplifier.
References Cited (Backward Citations)
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