Dual port access circuit

Claim 2

A dual port access enabling circuit CHARACTERISED BY (a) first and second main gates (G 1 ,G 2 ) to be supplied respectively with first and second input signals (CS1,CS2) contending for access, arranged so that the one main gate (say G 1 ) which happens to be supplied first in time with an input signal (say CS1=1) is . selectively enabled; (b) logic means (G 5 ,FF 1 )supplied with a signal (CE1PD) derived from an output signal (CE1P) of the selectively enabled gate (say G 1 ) for disabling the one gate (say G 1 ) immediately after lapse of a prescribed interval of time after it has been enabled and for immediately subsequently maintaining it disabled until the output signal (say CS1) to that gate (say G 1 ) terminates; and FURTHER CHARACTERISED BY (c) gating means (G 3 ,G 4 ) for selectively imbalancing the main gates (G 1 ,G 2 ) when the latter gates (G 1 ,G 2 ) tend toward an intermediate state caused by simultaneous initiation of the first and second input signals (CS1=CS2=1).

Claim 3

A circuit as claimed in claim 1, wherein the first and second main gates comprise cross-coupled, triple input main combinational logic elements; and the logic means includes first and second bistable logic elements(FF1,FF2) each respectively connected for delivering to a separate input terminal (A 2 ,B 2 ) of the first and second main logic elements (G 1 ,G 2 ), respectively, first and second priority status signals (Q1,Q2) representative of the instantaneous priority of access status of the access request signals ( CS1 =0, CS2 =0).

Claim 4

A circuit as claimed in claim 2, in which each of the main combinational logic elements (G 1 ,G 2 ) is a NAND gate.

Claim 5

A circuit as claimed in claim 2 or 3, wherein the gating means for selectively imbalancing the main gates comprises (a) first and second cross-coupled, triple input, auxiliary combinational logic elements (G 3 G 4 ), both having significantly weaker output driving strengths, respectively, than those of the first and second main logic elements (G 1 ,G 2 ), an output terminal, respectively, of the first and second auxiliary logic elements (G 3 ,G 4 ) being separately connected to the output terminal of the first and of the second main logic element (G 1 ,G 2 ), respectively, and an input terminal of the first and of the second auxiliary logic elements (G 3 ,G 4 ) being separately connected for receiving, respectively, the first and the second priority signals (Q1,Q2); and (b) first and second delay elements (Δ1,Δ2) having mutually different delay characteristics and being connected so as to deliver a differently delayed signal representative (CSID,CS2DD) of the first and of the second access request signal (CS1=0,CS2=0), respectively, to an input terminal of the respective one of the third and the fourth auxiliary logic elements (G 3 ,G 4 ).

Claim 6

A circuit as claimed in claim 4, in-which each of the auxiliary logic elements (G 3 ,G 4 ) is a NAND gate.

Claim 7

A circuit as claimed in claim 4 or 5, including first and second mutually cross-coupled gating elements (M535,M536) each having a controlled path separately connected respectively to the first and second nodes (N 1 ,N 2 ).

Claim 8

A circuit as claimed in claim 6, in which: (a) each gating element comprises a transistor element; (b) each main logic element (G 1 ) comprises a main triplet of input transistors (M503,M505,M507) whose controlled paths are mutually connected in series with a separate load element (M501); and (c) each auxiliary logic element (G 3 ) comprises an auxiliary triplet of input transistors (M513,M515,M517) whose controlled paths are mutually connected in series with the respective one (N 1 ) of the first and second nodes (N 1 ,N 2 ).

Claim 9

A circuit as claimed in any of claims 4 to 7, including (a) third and fourth delay elements (Δ 3 ,Δ 4 ), having substantially equal delay characteristics and separately connected for receiving the respective signals at the first and second nodes (N 1 ,N 2 ), respectively, for producing first and second delayed output signals (CE1PD, CE2PD) representative of the respective signals at the first and second nodes (N 1 ,N 2 ), respectively, delayed by the third and fourth delay elements (Δ 3 , A 4 ) ' respectively; and (b) first and second NOR gates (G5,G6), each having an output terminal separately connected to the set input terminal (S) of a separate one of the flip-flops (FF 1 , FF 2 ) each such NOR gate (G 5 ,G 6 ) having a first input terminal separately connected for receiving a complementary end-of-cycle signal (EOC) from the target circuit, and each NOR gate (G 5 ,G 6 ) having a second input terminal separately connected for receiving, respectively, the first and second delayed output signals (CEIPD, CE2PD), respectively.

Claim 10

A circuit as claimed in claim 8, including means (I 3 ,I 4 ) for separately delivering, to the reset input terminal (R) of a separate one of each of the flip-flops (FF 1 , FF 2 ), a delayed signal ( CS1D , CS2D ). representative of a delayed separate one of the conflicting access request signals (CS1, CS2).