Patent US2867769A successfully refreshed from Google Patents.
EP0106201A2
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Display control circuit for reading display data from a video RAM constituted by a dynamic RAM, thereby refreshing memory cells of the video RAM
Assignee: Toshiba Corp
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Filing: 1983-09-20
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Granted: —
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Expires: 2003-09-20
Abstract
Abstract Disclosed is a display control circuit comprising a video RAM (16) for storing display pattern data for a screen that has one row comprised of several rasters, a read controller (20) for generating a reading address (comprised of a raster address and a memory address) and an address converter (18) for converting a part of the raster address and a part of the memory address to a row address and for converting the remaining reading address to a column address and supplying the row and column addresses to the video RAM (16). The address converter (18) assigns a part of the raster address to the lower bit locations of the row address.
Inventors
- 👤 Takatoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 00:29
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/22; G09G5/222
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
103 words
A display control circuit comprising: a video RAM (16) for storing display data for a screen whose row is constituted by several rasters; read controller means (20) for generating a reading address of said video RAM including a raster address representing the raster position in each row and a memory address representing the digit position in each raster; characterized by further comprising means (18) for converting the reading address to a row address and a column address such that the row address contains at least a portion of the raster address and supplying the row and column addresses to the video RAM (16).
Claim 2
Dependent Claim
103 words
A display control circuit comprising: a video RAM (16) for storing display data for a screen whose row is constituted by several rasters; read controller means (20) for generating a reading address of said video RAM including a raster address representing the raster position in each row and a memory address representing the digit position in each raster; characterized by further comprising means (18) for converting the reading address to a row address and a column address such that the row address contains at least a portion of the raster address and supplying the row and column addresses to the video RAM (16).
Claim 3
Dependent Claim
126 words
A display control circuit according to claim 1, characterized in that said video RAM (16) has a code refresh memory having matrix cells of N rows x I columns, the addressing space of said code refresh memory being divided into 2 areas (where 2 P ≧ N/M : M represents the number of digits per row), said 2 P areas being each stored with the same display character codes, and a character generator (22) supplied with an output code of said code refresh memory and an output raster address of said read controller means (20), said converting means (18) assigns at least P bits of the raster address to the row address, whereby the video RAM (16) as a whole is refreshed in a P-raster period.
Claim 4
Dependent Claim
94 words
A display control circuit according to claim 1, . characterized in that said video RAM (16) stores a character code and the display data of which one-bit data corresponds to one dot on the screen, the addressing space of said video RAM (16) is divided by the raster address, one row of said screen comprised of 2 M digits and said converting means (18) assigns lower M bits of the memory address and the raster address to the row address and also assigns the remaining bits of the reading address to the column address.
References Cited (Backward Citations)
No citation records indexed.
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