EP0106121A2
Expired / Lapsed
EP
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Video RAM write control apparatus
Assignee: Toshiba Corp
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Filing: 1983-09-07
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Granted: —
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Expires: 2003-09-07
Abstract
Abstract A video RAM write control apparatus comprises a video RAM (22) of byte access for storing dot pattern data, and a write circuit for supplying write data of one byte and a write enable signal to the video RAM (22). The video RAM (22) includes n (n being an arbitrary natural number) memory blocks, each consisting of 1 bit x N addresses (N being an arbitrary natural number), the same address being assigned to the n memory blocks. The write circuit includes a bit mask register (40) in which an n-bit bit mask pattern data having a flag in a specific bit is set, and NAND gates (NGO, ... , NG7) for supplying AND signals of an output of each bit of the bit mask register (40) and a write enable signal to the write enable terminal of each memory block.
Inventors
- 👤 Takatoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:45
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
A video RAM write control apparatus comprising a video RAM (22) for storing dot pattern data, and a control circuit for supplying n-bit (n being an arbitrary natural number) write data and a write enable signal to said video RAM (22), characterized in that said video RAM (22) includes n memories (MBO, ..., MB7) each consisting of 1 bit x N addresses (N being an arbitrary natural number), and said control circuit includes means (40, 104) for storing n-bit bit mask pattern data having a flag set in a specific bit and write means (NGO, ..., NG7) for supplying n-bit write data to said video RAM (22) and for supplying a write enable signal to those memories (MBO, ..., MB7) which are specified by an output bit mask pattern data of said storing means (40, 104).
Claim 2
Dependent Claim
136 words
A video RAM write control apparatus comprising a video RAM (22) for storing dot pattern data, and a control circuit for supplying n-bit (n being an arbitrary natural number) write data and a write enable signal to said video RAM (22), characterized in that said video RAM (22) includes n memories (MBO, ..., MB7) each consisting of 1 bit x N addresses (N being an arbitrary natural number), and said control circuit includes means (40, 104) for storing n-bit bit mask pattern data having a flag set in a specific bit and write means (NGO, ..., NG7) for supplying n-bit write data to said video RAM (22) and for supplying a write enable signal to those memories (MBO, ..., MB7) which are specified by an output bit mask pattern data of said storing means (40, 104).
Claim 3
Dependent Claim
32 words
A video RAM write control apparatus according to claim 1, characterized in that said storing means is a bit mask register (40) in which the n-bit bit mask pattern data is set.
Claim 4
Dependent Claim
47 words
A video RAM write control apparatus according to claim l, characterized in that said storing means includes a bit mask memory (106) for pre-storing kinds of bit mask pattern data and an address register (108) in which an address for said bit mask memory (106) is set.
Claim 5
Dependent Claim
50 words
A video RAM write control apparatus according to claim 3, characterized in that said storing means further includes a gate circuit (114) for inverting a bit mask pattern data output from said bit mask memory (106) and a circuit (110) for controlling the inverting operation of said gate circuit (114).
Claim 6
Dependent Claim
29 words
A video RAM write control apparatus according to claim 1, characterized in that a common address is assigned to each memory (MBO, ..., MB7) in said video RAM (22).
Claim 7
Dependent Claim
92 words
A video RAM write control apparatus according to claim 1, characterized in that said write means includes n AND gate circuits (NGO, ..., NG7), each of which has one input terminal to which an output of each bit of said memory means (40, 104) is supplied, and the other input terminal to which a write enable signal is supplied, and in which each of said n AND gate circuits executes the AND operation of both inputs and supplies the results to a write enable terminal of each memory (MBO, ..., MB7), respectively.
Claim 8
Dependent Claim
37 words
A video RAM write control apparatus according to claim 1, characterized in that said bit mask pattern data has data "1" set in a bit to be written and said write data is data of any value.
References Cited (Backward Citations)
No citation records indexed.
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