Patent US1533354A successfully refreshed from Google Patents.
EP0105755A2
Expired / Lapsed
EP
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Selective accessing in data processing systems
Assignee: Fujitsu Ltd
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Filing: 1983-09-30
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Granted: —
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Expires: 2003-09-30
Abstract
Abstract A semiconductor IC device such as a peripheral interface LSI device used in a data processing system comprises an address memory, for storing an individual chip address of the device itself, and a comparator for comparing an address signal, supplied to the device from an external circuit, with the content of the address memory. In a preliminary step, address data supplied to the device when in an initial setting status is stored in the address memory for use as the chip address of the device. The device enters a chip selected condition depending on the coincidence between an address signal, supplied thereto from the external circuit, and the content of the address memory. By repitition of the preliminary step the stored address can be changed to facilitate use of the device with a modified system.
Inventors
- 👤 Hitoshi Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669; G06F12/0676
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
112 words
A semiconductor integrated circuit device used in a data processing system and connected to a bus line, characterized in that said device comprises an address memory for storing a chip address of said device itself and a comparator for comparing an address signal input thereto from an external circuit and the content of said address memory, an address data existing on said bus line in an initial setting status being previously stored in said address memory as a chip address of said device, and said device entering a chip selected condition depending on the coincidence between an address signal input thereto from an external circuit and the content of said address memory.
Claim 2
Dependent Claim
112 words
A semiconductor integrated circuit device used in a data processing system and connected to a bus line, characterized in that said device comprises an address memory for storing a chip address of said device itself and a comparator for comparing an address signal input thereto from an external circuit and the content of said address memory, an address data existing on said bus line in an initial setting status being previously stored in said address memory as a chip address of said device, and said device entering a chip selected condition depending on the coincidence between an address signal input thereto from an external circuit and the content of said address memory.
Claim 3
Dependent Claim
52 words
A semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device is connected to a central processing unit of said data processing system via said bus line and a bus buffer inserted midway of said bus line, said bus buffer being turned off in said initial setting status.
Claim 4
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 2, wherein an address setting circuit is inserted between said semiconductor integrated circuit device and said bus buffer.
Claim 5
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 3, wherein said address setting circuit comprises at least one resistor connected between a signal line in said bus line and a voltage source or between said signal line and the ground.
Claim 6
Dependent Claim
38 words
A semiconductor integrated circuit device according to claim 3, wherein said address setting circuit comprises at least resistor and at least one switch which selectively connects said at least one resistor to a voltage source or the ground.
Claim 7
Dependent Claim
63 words
A semiconductor integrated circuit device according to claim 3, 4 or 5, wherein said address memory is rendered to a write-in status and said bus buffer is turned off at the same time by a reset signal sent from said central processing unit in said initial setting status, thereby writing in an address data from said address setting circuit to said address memory.
Claim 8
Dependent Claim
138 words
A data processing system including a plurality of integrated circuit devices and a control unit whereby the said devices can be accessed individually through the transmission of respective address signals along a signal bus of the system, characterised in that the said devices include respective address memories for storing individual address codes, the system includes means whereby respective individual address codes can be set selectively into the said address memories in a preliminary setting operation, and each of the said devices includes a comparator for comparing the address code stored in the address memory of the device with an addressing code received by way of the said signal bus and causing the device to be switched into a selected condition upon detection of coincidence between the received addressing code and the individual stored address code of the device.
Claim 9
Dependent Claim
138 words
A data processing system including a plurality of integrated circuit devices and a control unit whereby the said devices can be accessed individually through the transmission of respective address signals along a signal bus of the system, characterised in that the said devices include respective address memories for storing individual address codes, the system includes means whereby respective individual address codes can be set selectively into the said address memories in a preliminary setting operation, and each of the said devices includes a comparator for comparing the address code stored in the address memory of the device with an addressing code received by way of the said signal bus and causing the device to be switched into a selected condition upon detection of coincidence between the received addressing code and the individual stored address code of the device.
References Cited (Backward Citations)
No citation records indexed.
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