EP0104657A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1983-09-28
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Granted: —
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Expires: 2003-09-28
Abstract
Abstract In a semiconductor integrated circuit device having at least two logic blocks (112, 113, 114, 115, 116) each including at least two logic units (10, 12, 15) each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FETs are selectively arranged between the logic blocks and/or the logic units so as to shorten the critical path of a logic block.
Inventors
- 👤 Hideo Maejima
- 👤 Ikuro Masuda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 10:51
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/786; G11C5/00; G11C5/06; G11C5/063; G11C7/00; G11C7/12; G11C8/00; G11C8/06; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
86 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising: a plurality of logic blocks (112, 113, 114, 3.15, 116; 90', 900') each including a plurality of logic units (11, 13; 91' - 96') each having a plurality of MOS FET's; and coupling circuits (10, 12, 15) each inserted between the logic units of said logic blocks to transmit signal between the logic units; at least one of said coupling circuits having at least a portion thereof constructed by bipolar transistors.
Claim 2
Dependent Claim
86 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising: a plurality of logic blocks (112, 113, 114, 3.15, 116; 90', 900') each including a plurality of logic units (11, 13; 91' - 96') each having a plurality of MOS FET's; and coupling circuits (10, 12, 15) each inserted between the logic units of said logic blocks to transmit signal between the logic units; at least one of said coupling circuits having at least a portion thereof constructed by bipolar transistors.
Claim 3
Dependent Claim
34 words
A semiconductor integrated circuit device according to Claim 1 wherein'at least one of the logic units connected to said coupling circuit having the bipolar transistors have the MOS FET's thereof arranged in a matrix.
Claim 4
Dependent Claim
22 words
A semiconductor integrated circuit device according to Claim 1 wherein said logic units include an address decoder (11) and memory cells (13).
Claim 5
Dependent Claim
38 words
A semiconductor integrated circuit divice according to Claim 1 wherein said coupling circuit having the bipolar transistors includes one set of address drivers (10), word drivers (12), a pre- charging circuit (14), sense circuits and output buffers (16).
Claim 6
Dependent Claim
103 words
A semiconductor integrated circuit device according to Claim 1 wherein said coupling circuit having the bipolar transistors includes the sense circuits (15), each of said sense circuits including a first bipolar transistor connected to a control signal line and a corresponding bit line to charge the bit line at a high speed, a logic circuit constructed by MOS FET's connected to said control signal line and said bit line to produce a logical output, and a second bipolar transistor connected to said logic circuit and said bit line to discharge said bit line at a high speed in response to said logical output.
Claim 7
Dependent Claim
82 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising: a plurality of logic blocks (112, 113, 114, 115, 116; 90', 900') each including a plurality of logic units (11, 13; 91' - 95') each having a plurality of MOS FET's; and coupling circuits (10, 12, 15) each inserted between said logic blocks to transmit signals between the logic blocks; at least one of said coupling circuits having at least a portion thereof constructed by bipolar transistors.
Claim 8
Dependent Claim
82 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising: a plurality of logic blocks (112, 113, 114, 115, 116; 90', 900') each including a plurality of logic units (11, 13; 91' - 95') each having a plurality of MOS FET's; and coupling circuits (10, 12, 15) each inserted between said logic blocks to transmit signals between the logic blocks; at least one of said coupling circuits having at least a portion thereof constructed by bipolar transistors.
Claim 9
Dependent Claim
35 words
A semiconductor integrated circuit device according to Claim 6 wherein at least one of the logic blocks connected to said coupling circuit having the bipolar transistors have the MOS FET's thereof arranged in a matrix.
Claim 10
Dependent Claim
36 words
A semiconductor integrated circuit device according to Claim 6 wherein said logic block connected to said coupling circuit having the bipolar transistors includes at least one of ROM (112), RAM (113), processor (114) and timer (115).
Claim 11
Dependent Claim
60 words
A semiconductor integrated circuit device according to Claim 6 wherein said semiconductor integrated circuit device is a processor (100'), said processor comprising as the logic blocks a processing circuit (90') including at least one of ALU (91'), shifter (92'), operation registers (93'), input register (94') and output register (95') as the logic unit, and a microinstruction decoder control block (900').
Claim 12
Dependent Claim
87 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising. a plurality of logic blocks (112, 113, 114, 115, 116) each including a circuit portion for forming a critical path in the logic block; and coupling circuit means (10, 12, 15) for interconnecting said logic blocks; said coupling circuit means being connected to at least one of the circuit portion forming the critical paths in said logic blocks and including bipolar transistors for driving at least a portion of said circuit portions.
Claim 13
Dependent Claim
87 words
A semiconductor integrated circuit device formed on a major surface of a semiconductor substrate comprising. a plurality of logic blocks (112, 113, 114, 115, 116) each including a circuit portion for forming a critical path in the logic block; and coupling circuit means (10, 12, 15) for interconnecting said logic blocks; said coupling circuit means being connected to at least one of the circuit portion forming the critical paths in said logic blocks and including bipolar transistors for driving at least a portion of said circuit portions.
Claim 14
Dependent Claim
31 words
ll. A semiconductor integrated circuit device according to Claim 10 wherein said circuit portion forming the critical path driven bv said bipolar transistors is constructed by a plurality of MOS FET's.
Claim 15
Dependent Claim
20 words
A semiconductor integrated circuit device according to Claim 11 wherein said plurality of MOS FET's are arranged in a matrix.
Claim 16
Dependent Claim
36 words
A semiconductor integrated circuit device according to Claim 10 wherein said semiconductor integrated circuit device is a processor (100), said processor comprising as the logic blocks a processing circuit (90') and a microinstructioh control logic (900').
References Cited (Backward Citations)
No citation records indexed.
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