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EP0102773A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Delay circuit arrangements

Assignee: Sony Corp
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Filing: 1983-08-09
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Granted: —
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Expires: 2003-08-09
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Abstract

Abstract A delay circuit arrangement comprises modulating means (41A, 41 B) for effecting contour modulation of a video signal using a signal from a carrier oscillator (50) as a carrier, delay means (43) for delaying the modulated output of the modulating means (41A, 41B), a variable phase shifter (52) for phase shifting the carrier oscillator output signal, demodulating means (45A, 45B) for effecting demodulation by synchronous detection using the output of the variable phase shifter (52) as a synchronizing signal, an adder (47) for superimposing a reference signal on a first demodulated signal from the demodulating means (45A, 45B) corresponding to a first input signal to the modulating means (41A, 41B) and supplying the resultant signal as a second input signal to the modulating means (41A, 41 B), and control means (54, 55, 56) for controlling the amount of phase shift by the variable phase shifter (52) according to the reference signal demodulated by the demodulating means (45A, 45B), wherein the demodulating means (45A, 45B) produces a first demodulated signal delayed relative to the first input signal supplied to the modulating means (41A, 41B) by an amount determined by the delay means (43) and a second demodulated signal delayed relative to the first input signal by double the amount.

Inventors

  • 👤 Sadaaki C/O Patent Division Tanaka

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 17:40
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; H04N5/205; H04N5/208

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 207 words
1 A delay circuit arrangement comprising: modulating means (41A, 41B) for effecting contour modulation of a signal using a signal from a carrier oscillator (50) as a carrier; delay means (43) for delaying the modulation output of said modulating means (41A, 41B); variable phase shifting means (52) for phase shifting said carrier oscillator output signal; demodulating means (45A, 45B) for effecting demodulation by synchronous detection using the output of said variable phase shifting means (52) as a synchronizing signal; adding means (47) for superimposing a reference signal on a first demodulated signal from said demodulating means (45A, 45B) corresponding to a first input signal to said modulating means (41A, 41B) and supplying the resultant signal as a second input signal to said modulating means (41A, 41B); and control means (54, 55, 56) for controlling the amount of phase shift by said variable phase shifting means (52) according to the reference signal demodulated by said demodulating means (45A, 45B); said demodulating means (41A, 41B) producing a first demodulated signal delayed relative to said first input signal supplied to said modulating means (41A, 41B) by an amount determined by said delay means (43) and a second demodulated signal delayed relative to said first input signal by double said amount.
Claim 2
Dependent Claim 207 words
1 A delay circuit arrangement comprising: modulating means (41A, 41B) for effecting contour modulation of a signal using a signal from a carrier oscillator (50) as a carrier; delay means (43) for delaying the modulation output of said modulating means (41A, 41B); variable phase shifting means (52) for phase shifting said carrier oscillator output signal; demodulating means (45A, 45B) for effecting demodulation by synchronous detection using the output of said variable phase shifting means (52) as a synchronizing signal; adding means (47) for superimposing a reference signal on a first demodulated signal from said demodulating means (45A, 45B) corresponding to a first input signal to said modulating means (41A, 41B) and supplying the resultant signal as a second input signal to said modulating means (41A, 41B); and control means (54, 55, 56) for controlling the amount of phase shift by said variable phase shifting means (52) according to the reference signal demodulated by said demodulating means (45A, 45B); said demodulating means (41A, 41B) producing a first demodulated signal delayed relative to said first input signal supplied to said modulating means (41A, 41B) by an amount determined by said delay means (43) and a second demodulated signal delayed relative to said first input signal by double said amount.
Claim 3
Dependent Claim 53 words
2 A delay circuit arrangement according to claim 1 further comprising a gain controlled amplifier (44) with the gain thereof controlled according to the output of said demodulating means (45A, 45B), the delayed signal from said delaying means (43) being supplied to said demodulating means (45A, 45B) through said gain controlled amplifier (44).
Claim 4
Dependent Claim 25 words
3 A delay circuit arrangement according to claim 3 wherein the gain of said gain controlled amplifier (44) is controlled according to said reference signal.

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