EP0102618A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory circuit with power supply voltage detection means
Assignee: NEC Corp
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Filing: 1983-08-31
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Granted: —
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Expires: 2003-08-31
Abstract
Abstract @ A memory circuit provided with a control circuit which controls operations of the memory circuit in such a manner that the memory circuit is automatically set in a stand-by state when a value of a power voltage is reduced in absolute value irrespectively of a control signal from the outside and which consumes no DC current is disclosed. The control circuit comprises a load element coupled between first and second terminals, a series circuit of first and second field effect transistors coupled between the second terminal and a third terminal, the first transistor being controlled by the control signal, the second transistor being adapted to be conducting when a value of the power voltage is sufficient for allowing a normal access operation, a means for connecting the first terminal to one of the power voltage and a reference voltage, and a means for connecting the third terminal to the other of the power voltage and the reference voltage.
Inventors
- 👤 Takayuki Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 01:11
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/565; G05F1/569; G05F1/571; G06; G06F; G06F1/00; G06F1/26; G06F1/28; G11; G11C; G11C5/00; G11C5/14; G11C5/143; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
183 words
A memory circuit comprising a matrix of memory cells, circuit means for reading or writing information from or to said memory cells, an operation control terminal, a power voltage terminal, means coupled to said matrix and said power voltage terminal for supplying a power voltage to said memory cells, a detection means including a series connection of first and second field effect transistors, a gate of said first transistor being coupled to said operation control terminal, said second transistor detecting that a voltage value at said power voltage terminal is changed between a normal value and a value smaller in absolute value than said normal value, and means coupled to said detection means and to said circuit means for enabling said circuit means when a potential at said power voltage terminal is of said normal value and a potential at said operation control terminal is at a first logic level and for disenabling said circuit means when the potential at said power voltage terminal is of said smaller value and/or the potential at said operation control terminal is at a second logic level.
Claim 2
Dependent Claim
183 words
A memory circuit comprising a matrix of memory cells, circuit means for reading or writing information from or to said memory cells, an operation control terminal, a power voltage terminal, means coupled to said matrix and said power voltage terminal for supplying a power voltage to said memory cells, a detection means including a series connection of first and second field effect transistors, a gate of said first transistor being coupled to said operation control terminal, said second transistor detecting that a voltage value at said power voltage terminal is changed between a normal value and a value smaller in absolute value than said normal value, and means coupled to said detection means and to said circuit means for enabling said circuit means when a potential at said power voltage terminal is of said normal value and a potential at said operation control terminal is at a first logic level and for disenabling said circuit means when the potential at said power voltage terminal is of said smaller value and/or the potential at said operation control terminal is at a second logic level.
Claim 3
Dependent Claim
126 words
The memory circuit according to claim 1, in which said detection means further includes a load means connected in series with said series connection of said first and second transistors, means for connecting one end of the series circuit of said load means and said first and second transistors to said power voltage terminal, and means for connecting the other end of said series circuit to a reference voltage terminal, said enabling and disenabling means being coupled to the junction of said load means and said series connection of said first and second transistors and enabling said circuit means when both of said first and second transistors are conducting while disenabling said circuit means when at least one of said first and second transistors is non-conducting.
Claim 4
Dependent Claim
53 words
The memory circuit according to claim 1, further comprising a selection circuit for designating at least one of said memory cells, means for receiving a write control signal, and control means for controlling said circuit means so as to conduct a write operation when said write control signal is of its active level.
Claim 5
Dependent Claim
53 words
The memory circuit according to claim 1, further comprising a selection circuit for selecting at least one of said memory cells, means for receiving a write control signal, and control means for controlling said circuit means so as to conduct a read operation when said write control signal is of its inactive level.
Claim 6
Dependent Claim
66 words
The memory circuit according to claim 1, further comprising a plurality of address input terminals, a plurality of address inverter buffers, a plurality of gate means each coupled between one of said address input terminals and an input of the corresponding one of said address inverter buffers, and gate control means for controlling said gate means in response to the potential at said operation control circuit.
Claim 7
Dependent Claim
19 words
The memory circuit according to claim 2, in which said load means is composed a third field effect transistor.
Claim 8
Dependent Claim
115 words
The memory circuit according to claim 1, in which said circuit means includes means for receiving a write control signal, a read circuit for operatively reading data from a selected memory cell, a write circuit for operatively writing data to the selected memory cell, first control means for selectively enabling said write circuit only when the potential at said operation control terminal is at said first value and said write control signal is the level designating a write operation, and second control means for selectively enabling said read circuit only when the potential at said operation control terminal is at said first value and said write control signal is the level designating a read operation.
Claim 9
Dependent Claim
149 words
A memory circuit comprising an array of a plurality of memory cells, a peripheral circuit for conducting an accessing operation with respect to said memory cells, means for receiving a control signal and a control circuit for controlling said peripheral circuit in response both to said control signal and a value of a power voltage, said control circuit including a load element coupled between first and second terminals, a series circuit of first and second field effect transistors, said first transistor being controlled by said control signal, said second transistor being adapted to be conducting when said power voltage is at a first value sufficient for conducting a normal access operation to said memory cell, means for connecting said first terminal to one of said power voltage and a reference voltage, and means for connecting said third terminal to the other of said power voltage and said reference voltage.
Claim 10
Dependent Claim
149 words
A memory circuit comprising an array of a plurality of memory cells, a peripheral circuit for conducting an accessing operation with respect to said memory cells, means for receiving a control signal and a control circuit for controlling said peripheral circuit in response both to said control signal and a value of a power voltage, said control circuit including a load element coupled between first and second terminals, a series circuit of first and second field effect transistors, said first transistor being controlled by said control signal, said second transistor being adapted to be conducting when said power voltage is at a first value sufficient for conducting a normal access operation to said memory cell, means for connecting said first terminal to one of said power voltage and a reference voltage, and means for connecting said third terminal to the other of said power voltage and said reference voltage.
Claim 11
Dependent Claim
156 words
An integrated circuit chip comprising at least one logic circuit, means for receiving a chip selection signal, a power voltage terminal, detection means including a series connection of first and second field effect transistors, a gate of said first transistor being coupled to said receiving means, said second transistor detecting that a voltage value at said power voltage terminal is changed between a normal value and a value smaller in absolute value than said normal value, and enabling means coupled to said detection means and to said at least one logic circuit for enabing said at least one logic circuit when a potential at said power voltage terminal is of said normal value and said chip selection signal is at a first logic level and disenabling said at least one logic circuit when the potential at said power voltage terminal is of said smaller value and/or said chip selection signal is at a second logic level.
Claim 12
Dependent Claim
156 words
An integrated circuit chip comprising at least one logic circuit, means for receiving a chip selection signal, a power voltage terminal, detection means including a series connection of first and second field effect transistors, a gate of said first transistor being coupled to said receiving means, said second transistor detecting that a voltage value at said power voltage terminal is changed between a normal value and a value smaller in absolute value than said normal value, and enabling means coupled to said detection means and to said at least one logic circuit for enabing said at least one logic circuit when a potential at said power voltage terminal is of said normal value and said chip selection signal is at a first logic level and disenabling said at least one logic circuit when the potential at said power voltage terminal is of said smaller value and/or said chip selection signal is at a second logic level.
Claim 13
Dependent Claim
119 words
The integrated circuit chip according to claim 9, in which said detection means further includes a load means connected in series with said series connection of said first and second transistors, means for connecting one end of the series circuit of said load means and said series connection to said power voltage terminal, and means for connecting the other end of said series circuit to a reference voltage terminal, said enabling means being coupled to the junction of said load means and said series connection and enabling said at least one logic circuit when both of said first and second transistors are conducting while disenabling the same when at least one of said first and second transistors is non-conducting.
Claim 14
Dependent Claim
19 words
The circuit according to claim 9, in which said logic circuit includes a peripheral circuit for accessing memory cells.
References Cited (Backward Citations)
No citation records indexed.
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