Patent US1366249A successfully refreshed from Google Patents.
EP0102485A2
Expired / Lapsed
EP
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Semiconductor memory
Assignee: International Business Machines Corp
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Filing: 1983-07-13
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Granted: —
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Expires: 2003-07-13
Abstract
Abstract @ Circuits for a static memory, particularly for a read only memory are disclosed which has two precharge current supply devices connected to each bit line (B j ) to enable the fast precharging of the bit line while the address inputs are down, and which sense the voltage on a dummy bit line (10) and which controls an active load to turn on, thereby quickly charging the array bit line when all of the address inputs are down and the dummy bit line is charging. When one address input goes up and the dummy bit line starts discharging, the feedback circuit controls the active load to turn off, thereby stopping the precharge current to the array bit line.
Inventors
- 👤 Charles Noble Alcorn
- 👤 Durwood Reginald Murray
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 04:50
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
325 words
In a static memory circuit (Fig. 1) having a plurality of FET storage devices (S ij ) arranged into a plurality of rows and columns, with each storage device in each column having its gate selectively connected to a respective row's word line (W i ) in accordance with a desired storage pattern and each storage device in each row having its source/drain path connected between a respective column's data bit line (B.) and a first reference potential, a self-aligned precharge circuit which is characterized by a dummy bit line (10) connected through the source/ drain path of each of a plurality of dummy FET devices to said first reference potential (ground), each said dummy FET device (P.) having its gate connected to a respective one of said word lines (W i ), having a sensing node (12) connected through a dummy static load device (P 0 ) to a second reference potential (V dd ), for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines (W.), a plurality of active bit line FET load devices (T ij ), each having its source/drain path respectively connected between a corresponding one of said data bit lines and a second reference potential and having its gate connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines, a plurality of static bit line load devices (T 2j ), each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active FET loads are turned off; whereby the data bit lines (B.) are precharged only between consecutive word line signals.
Claim 2
Dependent Claim
325 words
In a static memory circuit (Fig. 1) having a plurality of FET storage devices (S ij ) arranged into a plurality of rows and columns, with each storage device in each column having its gate selectively connected to a respective row's word line (W i ) in accordance with a desired storage pattern and each storage device in each row having its source/drain path connected between a respective column's data bit line (B.) and a first reference potential, a self-aligned precharge circuit which is characterized by a dummy bit line (10) connected through the source/ drain path of each of a plurality of dummy FET devices to said first reference potential (ground), each said dummy FET device (P.) having its gate connected to a respective one of said word lines (W i ), having a sensing node (12) connected through a dummy static load device (P 0 ) to a second reference potential (V dd ), for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines (W.), a plurality of active bit line FET load devices (T ij ), each having its source/drain path respectively connected between a corresponding one of said data bit lines and a second reference potential and having its gate connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines, a plurality of static bit line load devices (T 2j ), each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active FET loads are turned off; whereby the data bit lines (B.) are precharged only between consecutive word line signals.
Claim 3
Dependent Claim
15 words
The circuit of claim 1, wherein said FET devices (S..) are N channel FET devices.
Claim 4
Dependent Claim
21 words
The circuit of claim 2, wherein said dummy static load device (P.) is an N channel, depletion mode FET load device.
Claim 5
Dependent Claim
25 words
The circuit of claim 3, wherein each of said plurality of dummy FET devices (P i ) is an N channel, enhancement mode FET device.
Claim 6
Dependent Claim
25 words
The circuit of claim 2, characterized in that the plurality of active bit line FET load devices is an N channel, enhancement mode FET device.
Claim 7
Dependent Claim
25 words
The circuit of claim 5, characterized in that the plurality of static bit line load devices is an N channel, depletion mode FET load device.
Claim 8
Dependent Claim
22 words
The circuit of claim 6, characterized in that the dummy static load device is an N channel, depletion mode FET load device.
Claim 9
Dependent Claim
24 words
The circuit of claim 7, characterized in that each of said plurality of dummy FET devices is an N channel, enhancement mode FET device.
Claim 10
Dependent Claim
22 words
The circuit of claim 8, characterized in that the plurality of FET storage devices is an N channel, enhancement mode FET device.
Claim 11
Dependent Claim
15 words
The circuit of claim 1, characterized in that FET devices are P channel FET devices.
Claim 12
Dependent Claim
305 words
In a read only memory circuit having a plurality of N channel FET storage devices arranged into a plurality of rows and columns, with each storage device in each column having its gate selectively connected to a respective row's word line in accordance with a desired storage pattern and each storage device in each row having its source/drain path connected between a respective column's data bit line and a first reference potential, a self-aligned precharge circuit, characterized by a dummy bit line connected through the source/drain path of each of a plurality of dummy N channel FET devices to said first reference potential, each said dummy FET device having its gate connected to a respective one of said word lines, having a sensing node connected through a dummy P channel FET static load device to a second reference potential, for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines; a plurality of active bit line P channel FET load devices, each having its source/drain path respectively connected between a corresponding one of said data bit lines and said second reference potential and having its gate connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines; a plurality of static P channel FET bit line load devices, each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active FET loads are turned off; whereby the data bit lines are precharged only between consecutive word line signals.
Claim 13
Dependent Claim
305 words
In a read only memory circuit having a plurality of N channel FET storage devices arranged into a plurality of rows and columns, with each storage device in each column having its gate selectively connected to a respective row's word line in accordance with a desired storage pattern and each storage device in each row having its source/drain path connected between a respective column's data bit line and a first reference potential, a self-aligned precharge circuit, characterized by a dummy bit line connected through the source/drain path of each of a plurality of dummy N channel FET devices to said first reference potential, each said dummy FET device having its gate connected to a respective one of said word lines, having a sensing node connected through a dummy P channel FET static load device to a second reference potential, for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines; a plurality of active bit line P channel FET load devices, each having its source/drain path respectively connected between a corresponding one of said data bit lines and said second reference potential and having its gate connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines; a plurality of static P channel FET bit line load devices, each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active FET loads are turned off; whereby the data bit lines are precharged only between consecutive word line signals.
Claim 14
Dependent Claim
297 words
In a read only memory circuit having a plurality of NPN bipolar transistor storage devices arranged into a plurality of rows and columns, with each storage device in each column having its base selectively connected to a respective row's word line in accordance with a desired storage pattern and each storage device in each row having its emitter-collector path connected between a respective column's data bit line and a first reference potential, a self-aligned precharge circuit, characterized by a dummy bit line connected through the emitter-collector path of each of a plurality of dummy NPN bipolar transistor devices to said first reference potential, each said dummy transistor device having its gate connected to a respective one of said word lines, having a sensing node connected through a dummy load device to a second reference potential, for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines; a plurality of active bit line NPN bipolar transistor load devices, each having its emitter-collector path respectively connected between a corresponding one of said data bit lines and said second reference potential and having its base connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines; a plurality of bit line load devices, each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active transistor loads are turned off; whereby the data bit lines are precharged only between consecutive word line signals.
Claim 15
Dependent Claim
297 words
In a read only memory circuit having a plurality of NPN bipolar transistor storage devices arranged into a plurality of rows and columns, with each storage device in each column having its base selectively connected to a respective row's word line in accordance with a desired storage pattern and each storage device in each row having its emitter-collector path connected between a respective column's data bit line and a first reference potential, a self-aligned precharge circuit, characterized by a dummy bit line connected through the emitter-collector path of each of a plurality of dummy NPN bipolar transistor devices to said first reference potential, each said dummy transistor device having its gate connected to a respective one of said word lines, having a sensing node connected through a dummy load device to a second reference potential, for sensing at said sensing node the occurrence of a signal on any of said plurality of word lines; a plurality of active bit line NPN bipolar transistor load devices, each having its emitter-collector path respectively connected between a corresponding one of said data bit lines and said second reference potential and having its base connected to said sensing node of said dummy bit line, for conducting precharge current to said corresponding data bit lines in the absence of said signal on any of said word lines and terminating the conduction of said precharge current when said signal is present on any one of said word lines; a plurality of bit line load devices, each respectively connected between a corresponding one of said data bit lines and said second reference potential, for maintaining said data bit lines at a precharged potential after said active transistor loads are turned off; whereby the data bit lines are precharged only between consecutive word line signals.
References Cited (Backward Citations)
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