EP0102218A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Sense amplifier circuit for semiconductor memory
Assignee: Toshiba Corp
•
Filing: 1983-08-16
•
Granted: —
•
Expires: 2003-08-16
Abstract
Abstract A sense amplifier circuit for a semiconductor memory device, which includes a pair of MOS transistors (13, 13') connected to a supply line (V pp ) each of which forms the load for a respective bipolar sensing transistor (15, 15'). The bipolar transistors are provided with a constant current source which also comprises an MOS transistor.
Inventors
- 👤 Junichi Patent Div. Tokyo Shibaura Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 20:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
128 words
A sense amplifier circuit comprising a first and second sensing transistors (15, 15'), first and second load elements (13, 13') connected to said first and second sensing transistors respectively, a constant voltage supply (V DD ) connected to said first and second load elements, first and second input terminals (3, 4) coupled to control electrodes of said first and second sensing transistors respectively, first and second output terminals (V o ) coupled to connecting points of said first and second sensing transistors and load elements respectively, and a constant current supply (14) connected to said first and second sensing transistors, characterised in that each said sensing transistor is a bipolar transistor, each said load element is an MOS transistor and said constant current supply comprises an MOS transistor.
Claim 2
Dependent Claim
128 words
A sense amplifier circuit comprising a first and second sensing transistors (15, 15'), first and second load elements (13, 13') connected to said first and second sensing transistors respectively, a constant voltage supply (V DD ) connected to said first and second load elements, first and second input terminals (3, 4) coupled to control electrodes of said first and second sensing transistors respectively, first and second output terminals (V o ) coupled to connecting points of said first and second sensing transistors and load elements respectively, and a constant current supply (14) connected to said first and second sensing transistors, characterised in that each said sensing transistor is a bipolar transistor, each said load element is an MOS transistor and said constant current supply comprises an MOS transistor.
Claim 3
Dependent Claim
83 words
A sense amplifier circuit according to claim 1 further characterised in that; each said load element (13, 13') is a P channel MOS transistor and said constant current supply (14) comprises an N channel MOS transistor and each said bipolar transistor (15, 15') is an NPN type bipolar transistor, the base electrode of each said bipolar transistor being connected to said input terminal (3 or 4), the emitter electrode to said constant current supply (14) and the collector electrode to said output terminal.
Claim 4
Dependent Claim
53 words
A sense amplifier. circuit according to claims 1 or 2 further characterised in that; said first and second sensing transistors are connected to third and fourth bipolar transistors (16, 16') respectively so as to form Darlington pairs, said third and fourth bipolar transistors being connected to said first and second input terminals respectively.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.