EP0101960A1
Expired / Lapsed
EP
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Method of manufacturing a semiconductor device having a self-aligned gate electrode
Assignee: Hitachi Ltd
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Filing: 1983-07-29
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Granted: —
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Expires: 2003-07-29
Abstract
Abstract In manufacturing a field effect transistor, a pattern which has a wider upper layer (11, 18) and a narrower lower layer (12, 19) is formed at a gate electrode position. Using the pattern as a mask, first (2) and second (3) impurity regions are formed on both the sides of a gate region (4) by ion implantation. Subsequently, at least the lower layer (12, 15) is buried in a material (13, 16), such as an organic high polymer material, having a selectivity in etching characteristics with respect to the pattern material. After removing the lower layer (12, 19), an electrode material (15, 71) is embedded in the resulting hole (14) so as to form a gate electrode (7, 81).
Inventors
- 👤 Masaru Miyazaki
- 👤 Susumu Takahashi
- 👤 Takahiro Kohashi
- 👤 Kiichi Ueyanagi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 23:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D64/00; H10D64/01; H10D64/011; H10P; H10P76/00; H10P76/20; H10P76/202
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
194 words
A method of manufacturing a semiconductor device comprising the steps of forming a pattern (1 0 ) at a gate electrode position on a predetermined semiconductor body (1), the pattern including at least two regions of an upper layer (11, 18) and a lower layer (12, 19), the upper layer (11, 18) being wider than the lower layer (12, 19); forming first (2) and second (3) impurity regions on both sides of a gate region (4) by ion implantation by'employing at least the pattern (1 0 ) as a mask; forming a layer (13, 16) of a material on the substrate in a manner to bury at least the lower layer (12), the material (13, 16) having a selectivity in etching characteristics with respect to a material of the pattern;-subsequently removing said pattern (10) and forming a reversal pattern of at least said lower layer (12, 19); evaporating a metal layer (15, 71) for a gate electrode (7, 81); removing the material layer (13; 16) having the selectivity in etching characteristics with respect to the pattern material; and forming respective electrodes (5, 6) in contact with said first (2) and second (3) impurity regions.
Claim 2
Independent Claim
194 words
A method of manufacturing a semiconductor device comprising the steps of forming a pattern (1 0 ) at a gate electrode position on a predetermined semiconductor body (1), the pattern including at least two regions of an upper layer (11, 18) and a lower layer (12, 19), the upper layer (11, 18) being wider than the lower layer (12, 19); forming first (2) and second (3) impurity regions on both sides of a gate region (4) by ion implantation by'employing at least the pattern (1 0 ) as a mask; forming a layer (13, 16) of a material on the substrate in a manner to bury at least the lower layer (12), the material (13, 16) having a selectivity in etching characteristics with respect to a material of the pattern;-subsequently removing said pattern (10) and forming a reversal pattern of at least said lower layer (12, 19); evaporating a metal layer (15, 71) for a gate electrode (7, 81); removing the material layer (13; 16) having the selectivity in etching characteristics with respect to the pattern material; and forming respective electrodes (5, 6) in contact with said first (2) and second (3) impurity regions.
Claim 3
Dependent Claim
35 words
A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor body (1) is made of a semi-insulating semiconductor substrate which is provided with an active region (4) in its upper region.
Claim 4
Dependent Claim
46 words
A method of manufacturing a semiconductor device according to claim 1 or claim 2, wherein after forming an insulator layer (8) on said semiconductor body, the pattern having said upper layer (11, 18) and said lower layer (12, 19) is formed at the gate electrode position.
Claim 5
Independent Claim
44 words
A method of manufacturing a semiconductor device according to any of the claims 1.to 3, wherein the formation of the material layer (16) having the selectivity in etching characteristics with respect to the pattern material is performed after removing said upper layer (11, 19).
Claim 6
Dependent Claim
51 words
A method of-manufacturing a semiconductor device according to claim 2 or claim 3, wherein the formation of the material layer (13, 16) having the selectivity in etching characteristics with respect to the pattern material is performed after removing said upper layer (11, 18) and further forming a second insulator layer (17).
Claim 7
Independent Claim
60 words
A method of manufacturing a semiconductor device according to any of the claims 1 to 3, wherein said upper layer (11, 18) and said lower layer (12, 19) are inorganic materials having selectivities in etching characteristics therebetween, and the material (13, 16) having the selectivities in etching characteristics with respect to the pattern materials is an organic high polymer resin.
Claim 8
Dependent Claim
49 words
A method of manufacturing a semiconductor device according to claim 1 or claim 2, wherein after forming said first (2) and second impurity regions (3), a metal layer (41) is evaporated and is processed into electrodes (5, 6) respectively lying in contact with said first and second impurity regions.
References Cited (Backward Citations)
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