EP0101791A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Multi-layer circuitry
Assignee: Olin Corp
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Filing: 1983-04-27
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Granted: —
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Expires: 2003-04-27
Abstract
Abstract Multi-layer circuitry 10 incorporating electronic elements 12-16 is disclosed. The circuitry comprises a plurality of layers including a metal or alloy substrate 24 formed with a recess 26 on one surface 28. An electronic element 12 is positioned within the recess and a second electronic element 14 is positioned on the surface 28. Also, a first dielectric material layer 30 is disposed on the surface 28. Further, a first layered conductive circuit pattern 32 overlies the first dielectric material layer 30 so as to provide circuitry over a substantial portion of the substrate 24. The first circuit pattern is electrically connected to the first electronic element. The first circuit pattern also has a cavity 36 therein for receiving the second electronic element 14. A second layered conductive pattern 38 overlies at least a portion of the first layered conductive circuit pattern 32 and the second electronic element 14 and is electrically connected to the second electronic element. A second dielectric material layer 40 is disposed between the first and second layered conductive circuit patterns 32 and 38 so that these circuit patterns are bonded to and isolated from each other.
Inventors
- 👤 Sheldon H. Butt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:46
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0201; H05K1/0203; H05K1/18; H05K1/182; H05K1/185; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/6875; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09745; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10674; H05K2203/00; H05K2203/04; H05K2203/049; H05K3/00; H05K3/46; H05K3/4602; H05K3/4608; H05K3/4644; H10W70/682; H10W90/00; Y; Y10; Y10T; Y10T428/00; Y10T428/12; Y10T428/12389; Y10T428/12396
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
219 words
Multi-layer circuitry 10 incorporating electronic elements 12-16, characterized by: a metal or alloy substrate 24, said substrate formed with at least a first recess 26 on a surface 28 thereof, said substrate further having at least a first electronic element 12 positioned within said recess and at least a second electronic element -14 positioned on said surface 28; a first dielectric material layer 30 disposed on said surface 28; a first layered conductive circuit pattern means 32 overlying said first dielectric material layer 30 to provide circuitry over a substantial portion of said substrate 24, said first circuit pattern means being electrically connected to said at least first electronic element 12, said first circuit pattern means further having at least a first cavity 36 therein for receiving said at least a second electronic element 14; at least a second layered conductive circuit pattern means 38 and overlying at least a portion of said first layered conductive circuit pattern means 32 and said at least a second electronic element 14 for electrical connection to said at least a second electronic element; and at least a second dielectric material layer 40 disposed between said first and second layered conductive circuit pattern means 32 and 38 whereby said first and second circuit pattern means are bonded to and insulated from each other.
Claim 2
Dependent Claim
219 words
Multi-layer circuitry 10 incorporating electronic elements 12-16, characterized by: a metal or alloy substrate 24, said substrate formed with at least a first recess 26 on a surface 28 thereof, said substrate further having at least a first electronic element 12 positioned within said recess and at least a second electronic element -14 positioned on said surface 28; a first dielectric material layer 30 disposed on said surface 28; a first layered conductive circuit pattern means 32 overlying said first dielectric material layer 30 to provide circuitry over a substantial portion of said substrate 24, said first circuit pattern means being electrically connected to said at least first electronic element 12, said first circuit pattern means further having at least a first cavity 36 therein for receiving said at least a second electronic element 14; at least a second layered conductive circuit pattern means 38 and overlying at least a portion of said first layered conductive circuit pattern means 32 and said at least a second electronic element 14 for electrical connection to said at least a second electronic element; and at least a second dielectric material layer 40 disposed between said first and second layered conductive circuit pattern means 32 and 38 whereby said first and second circuit pattern means are bonded to and insulated from each other.
Claim 3
Dependent Claim
68 words
The circuitry of claim 1 characterized in that said second layered conductive circuit pattern means 38 has at least a second cavity 97 therein, and further including a metal or alloy pedestal 96 positioned within said first cavity 36 and under said second cavity 97 and affixed to said substrate, at least a third electronic element 16 supported by said pedestal and positioned within said second cavity 97.
Claim 4
Dependent Claim
47 words
The circuitry of claim 2 further characterized by a third layered conductive circuit pattern means 22 overlying said second layered conductive circuit pattern means 20 and said third electronic element 16, said third circuit pattern means being electrically connected to said at least a third electronic element.
Claim 5
Dependent Claim
98 words
The circuitry of any of claims 1 to 3 characterized in that said first layered conductive circuit pattern means includes: a first metal or alloy foil 50 electrically connected to said first electronic element 12; a first printed circuit metal or alloy component 32; a first intermediate dielectric material layer 52 interposed between and bonded to said first metal or alloy foil and said first printed circuit metal or alloy component whereby said first foil and said first circuit component are insulated from each other; and means for electrically connecting said first foil to said first circuit component.
Claim 6
Dependent Claim
97 words
The circuitry of any of claims 1 to 4 characterized in that said at least a second layered conductive circuit pattern means includes: a second metal or alloy foil electrically connected to said second electronic element; a second printed circuit metal or alloy component; a second intermediate dielectric material layer interposed between and bonded to said second metal or alloy foil and said second printed circuit metal or alloy component whereby said second foil and said second circuit component are insulated from each other; and means for electrically connecting said second foil to said second circuit component.
Claim 7
Dependent Claim
33 words
The circuitry of any of claims 1 to 5 characterized in that said first and second dielectric material layers and said first and second dielectric materials are formed of a thin refractory oxide.
Claim 8
Dependent Claim
36 words
The circuitry of claim 5 or.6 characterized in that said substrate, said first and second printed circuit alloy components, and said first and second alloy foils comprise: 2 to 10% aluminum and the balance essentially copper.
Claim 9
Dependent Claim
27 words
The circuitry of any of claims 3 to 7 further including a cover plate means 100 for covering said first, second, and third layered conductive pattern means.
Claim 10
Dependent Claim
199 words
The process of forming multi-layer circuitry 10 incorporating electronic elements 12-16, characterized by the steps of: providing a metal or alloy substrate 24 having a recess 26 on a surface 28 thereof; positioning a first electronic element 12 within said recess and a second electronic element 14 on said surface 28; disposing a first dielectric material layer 30 on said surface 28; overlying said first dielectric material layer 30 with a first layered conductive circuit pattern 32 to provide circuitry over a substantial portion of said substrate; electrically connecting said first circuit pattern to said first electronic element 12; providing a first cavity 36 in said first circuit pattern for receiving a second electronic element 14; overlying a portion of said first layered conductive circuit pattern 32 and said at least a second electronic element 14 with at least a second layered conductive circuit pattern 38; electrically connecting said second layered conductive circuit pattern to said at least a second electronic element; and disposing at least a second dielectric material layer 40 between said first and second layered conductive circuit patterns 32 and 38 whereby said first and second circuit patterns are bonded to and insulated from each other.
Claim 11
Dependent Claim
199 words
The process of forming multi-layer circuitry 10 incorporating electronic elements 12-16, characterized by the steps of: providing a metal or alloy substrate 24 having a recess 26 on a surface 28 thereof; positioning a first electronic element 12 within said recess and a second electronic element 14 on said surface 28; disposing a first dielectric material layer 30 on said surface 28; overlying said first dielectric material layer 30 with a first layered conductive circuit pattern 32 to provide circuitry over a substantial portion of said substrate; electrically connecting said first circuit pattern to said first electronic element 12; providing a first cavity 36 in said first circuit pattern for receiving a second electronic element 14; overlying a portion of said first layered conductive circuit pattern 32 and said at least a second electronic element 14 with at least a second layered conductive circuit pattern 38; electrically connecting said second layered conductive circuit pattern to said at least a second electronic element; and disposing at least a second dielectric material layer 40 between said first and second layered conductive circuit patterns 32 and 38 whereby said first and second circuit patterns are bonded to and insulated from each other.
Claim 12
Dependent Claim
61 words
The process of claim 9 further characterized by the steps of: providing a second cavity 97 in said second layered conductive circuit pattern 38; affixing a metal or alloy pedestal 96 to said substrate within said first cavity 36 and under said second cavity 97; and supporting at least a third electronic element 16 upon said pedestal within said second cavity.
Claim 13
Dependent Claim
49 words
The process of claim 10 further characterized by the steps of: overlying said at least a second layered conductive circuit pattern 38 and said third electronic element with a third layered conductive circuit pattern 22; and electrically connecting said third circuit pattern to at least said third electronic element.
Claim 14
Dependent Claim
110 words
The process of any of claims 9 to 11 characterized in that said step of providing said first layered conductive circuit pattern includes the steps of: providing a first metal or alloy foil 50; electrically connecting said first metal or alloy foil to said first electronic element 12; providing a first printed circuit metal or alloy component 32; interposing a first intermediate dielectric material layer 52 between said first metal or alloy foil and said first printed circuit metal or alloy component whereby said first foil and said first circuit component are bonded to and insulated from each other; and electrically connecting said first foil to said first circuit component.
Claim 15
Dependent Claim
102 words
The process of any of claims 9 to 12 characterized in that said step of providing at least a second layered conductive circuit pattern includes: providing a second metal or alloy foil; electrically connecting said second foil to said second electronic element; providing a second printed circuit metal or alloy component; interposing a second intermediate dielectric material layer between said second metal or alloy foil and said second printed circuit metal or alloy component whereby said second foil and said second circuit component are. bonded to and insulated from each other; and electrically connecting said second foil to said' second circuit component.
Claim 16
Dependent Claim
33 words
The process of any of claims 9 to 13 characterized in that said first and second dielectric material layers and said first and second dielectric materials are formed of a thin refractory oxide.
Claim 17
Dependent Claim
35 words
The process of claim 13 or 14 characterized in that said substrate, said first and second printed circuit alloy components, and said first and second alloy foils comprise 2-10% aluminum and the balance essentially copper.
Claim 18
Dependent Claim
28 words
The process of any of claims 12 to 15 charaterized by the step of covering said first, second, and third conductive pattern means with a cover plate 100.
References Cited (Backward Citations)
No citation records indexed.
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