EP0100103A1
Expired / Lapsed
EP
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A pulse width modulation circuit and an analog product forming integration circuit using such modulation circuit
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1983-07-27
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Granted: —
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Expires: 2003-07-27
Abstract
Abstract A pulse width modulation circuit is capable of cancelling the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits (FF3, L1, L2) to an existing pulse width modulation circuit (10, CP3). Such pulse width modulation circuit is used preferably in an integration circuit forming the product of two analog signals.The offset of the triangular wave signal (VA) is cancelled by inverting either the triangular wave signal with respect to the input signal or the input signal with respect to the triangular wave signal, in every predetermined period. To this end, the circuit eliminates the offset of a comparator (CP3) by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.
Inventors
- 👤 Katsuaki Takagi
- 👤 Yuzo Kita
- 👤 Yoshimune Hagiwara
- 👤 Kazuyoshi Ogawa
- 👤 Hideo Hara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 17:26
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/82; H03K; H03K7/00; H03K7/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
136 words
A pulse width modulation circuit comprising: signal generation means (10) for generating a triangular wave signal having a predetermined frequency; clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal; comparison means (CP3) for comparing two input signals to generate binary signal and receiving said triangular wave signal at one of its input terminals; switch means (SW3) for changing over an analog signal to be used for pulse width modulation in response to said clock signal and its inversion signal and applying said inversion signal to the second input terminal of said comparison means (CP3); and inversion means (L2) for selectively responding to the first value of said clock signal and inverting the output of said comparison means (CP3).
Claim 2
Dependent Claim
136 words
A pulse width modulation circuit comprising: signal generation means (10) for generating a triangular wave signal having a predetermined frequency; clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal; comparison means (CP3) for comparing two input signals to generate binary signal and receiving said triangular wave signal at one of its input terminals; switch means (SW3) for changing over an analog signal to be used for pulse width modulation in response to said clock signal and its inversion signal and applying said inversion signal to the second input terminal of said comparison means (CP3); and inversion means (L2) for selectively responding to the first value of said clock signal and inverting the output of said comparison means (CP3).
Claim 3
Dependent Claim
158 words
A pulse width modulation circuit comprising: means (10, 30) for generating a triangular wave'signal having a predetermined frequency and its inversion signal; clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal; comparison means (CP3) for comparing two input signals and producing a binary signal; switch means (SW4, SW5) for applying said triangular wave signal and an analog signal to be used for pulse width modulation to the first and second input terminals of said comparison means (CP3), respectively, in response to the first value of said clock signal, and applying said analog signal and said inverted triangular wave signal to the first and second input terminals, respectively, in response to the second value of said clock signal; and inversion means; (L2) for inverting the output of said comparison means selectively in response to the first value of said clock signal.
Claim 4
Dependent Claim
158 words
A pulse width modulation circuit comprising: means (10, 30) for generating a triangular wave'signal having a predetermined frequency and its inversion signal; clock signal generation means (FF3) for generating a clock signal taking alternately first and second values in a predetermined period in synchronism with said triangular wave signal; comparison means (CP3) for comparing two input signals and producing a binary signal; switch means (SW4, SW5) for applying said triangular wave signal and an analog signal to be used for pulse width modulation to the first and second input terminals of said comparison means (CP3), respectively, in response to the first value of said clock signal, and applying said analog signal and said inverted triangular wave signal to the first and second input terminals, respectively, in response to the second value of said clock signal; and inversion means; (L2) for inverting the output of said comparison means selectively in response to the first value of said clock signal.
Claim 5
Dependent Claim
33 words
The pulse width modulation circuit as defined in claim 1 or 2, wherein said clock signal generation means (FF3) include means for dividing the frequency of said triangular wave signal by an integer.
Claim 6
Dependent Claim
37 words
The pulse width modulation circuit as defined'in any of claims 1 to 3, wherein said inversion means is an exclusive-OR circuit (L2) to which the output of said comparison means (CP3) and said clock signal are applied.
Claim 7
Dependent Claim
63 words
An analog product forming integration circuit comprising: a pulse width modulation circuit as defined in any of claims 1 to 4; and operation means (20) including selection means (SW2) for selecting the second analog signal and the inversion signal of said second analog signal in response to the output of said inversion means (L2), and means for integrating (INT2) the signal thus selected.
Claim 8
Dependent Claim
32 words
The integration circuit as defined in claim 5, wherein said operation means (20) further include means for generating a pulse whenever the output of said integration means (INT2) reaches a predetermined value.
Claim 9
Dependent Claim
97 words
The integration circuit as defined in claim 5 or 6, wherein said operation means further include first means (CP4, CP5) for comparing the output of said integration means with first and second reference values, second means (L1) for inverting the output of said inversion means (L2), disposed between said selection means (SW2) and said inversion means (L2), and third means (FF2) for. controlling said second means (L1) so that said second means alternately effect inversion and non-inversion in synchronism with detection of the coincidence with the first and second reference value by said first means (CP4, CP5).
Claim 10
Dependent Claim
64 words
The integration circuit as defined in claim 7, wherein said third means consist of flip-flop means (FF2) set alternately to first and second state whenever the coincidence is detected by said first means (CP4, CP5), and said second means consist of an exclusive-OR gate (L1) to which the output of said inversion means (L2) and the output of said flip-flop means (FF2) are applied.
References Cited (Backward Citations)
DE1512210B2
Cited
GB1560350A
Cited
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