Apparatus for adding first and second binary operands

Claim 1

Apparatus for adding first and second binary operands each having a nominal length of N bits and a carry-in signal, and for providing a sum output signal having N bits and a carry-out signal, said apparatus comprising: first logic means (231,232,233,234; 241,242,243, 244) having a first input coupled to a bit signal of the first operand (A o -A3) and a second input coupled to a bit signal of the second operand (BO-B 3 ) for providing one or more output.signals in response to predetermined logical operation; selective gating means (210, 211, 212, 213) having three inputs and an output, a first input of which provides a control input for receiving an output signal from the first logic means, a second input of which is for receiving a second signal and a third input of which is for receiving the carry-in signal, for providing the carry-out signal in response to a predetermined logical operation; and second logic means (245, 246, 247, 248) having a first input, and a second input for receiving an output signal from the first logic means for providing the sum output signal in response to a predetermined logical operation; the apparatus being characterized in that the second input of the selective gating means is connected to receive a bit signal of the second operand or a second output signal from the first logic means, and in that the first input of the second logic means is connected to receive the carry-in signal applied to the third input of the selective gating means.

Claim 8

An apparatus for adding first and second binary operands each having a nominal length of N bits and a carry-in signal, and for providing a sum output signal having N bits and a carry-out signal, said apparatus comprising: first logic means (241,242,243,244) having a first input coupled to a bit signal of the first operand (A (O-3) ) and a second input coupled to a bit signal of the second operand (B (O-3) ) for providing an output signal in response to predetermined logical operation; second logic means (245,246,247,248) having a first input for receiving the carry-in signal, and a second input whereby an output of the first logic means can be supplied thereto for providing the sum output signal in response to a predetermined logical operation; and selective gating means (210(211/212,213) having three inputs and an output, a first input providing a control input and another of said three inputs being provided for receiving the carry-in signal, whereby to provide the carry-out signal in response to a predetermined logical operation; the apparatus being characterized in that the second input of the second logic means is connected to the output of the first logic menas for providing the sum output signal as aforesaid, a second input of the selective gating means is connected to the second input of the first logic means for receiving the bit signal of the second operand, and said another of said three inputs provides the third input.

Claim 9

An apparatus for adding first and second binary operands each having a nominal length of N bits and a carry-in signal, and for providing a sum output signal having N bits and a carry-out signal, said apparatus comprising: first logic means (241,242,243,244) having a first input coupled to a bit signal of the first operand (A (O-3) ) and a second input coupled to a bit signal of the second operand (B (O-3) ) for providing an output signal in response to predetermined logical operation; second logic means (245,246,247,248) having a first input for receiving the carry-in signal, and a second input whereby an output of the first logic means can be supplied thereto for providing the sum output signal in response to a predetermined logical operation; and selective gating means (210(211/212,213) having three inputs and an output, a first input providing a control input and another of said three inputs being provided for receiving the carry-in signal, whereby to provide the carry-out signal in response to a predetermined logical operation; the apparatus being characterized in that the second input of the second logic means is connected to the output of the first logic menas for providing the sum output signal as aforesaid, a second input of the selective gating means is connected to the second input of the first logic means for receiving the bit signal of the second operand, and said another of said three inputs provides the third input.

Claim 10

An apparatus for adding first and second binary operands, each -aving a nominal length of N bits and a carry-in signal, and for providing a sum output signal having N bits and a carry-out signal, said apparatus comprising: N logic cells each for receiving a corresponding bit of each operand and providing a sum output signal, and a carry-out signal, each cell of the apparatus comprising first logic means comprising first and second gate means (231,241,232,242,233,243,234,244), each of which has a first input for receiving a corresponding bit signal of the first operand (Ao-A3) and a second input for receiving a corresponding bit signal of the second operand (B O -B 3 ), to provide first and second output signals respectively in response to a predetermined logical operation; selective gating means (210,211,212,213) having a first, control, input for receiving the second output signal from the second gate means, a second signal input for receiving the first output signal from the first gate means, and a third signal input for receiving the carry-in signal, for providing the carry-out signal in response to a predetermined logical operation; and second logic means (245,246,247,248) having a first input for receiving the carry-in signal, and a second input for receiving the second output signal of the second gate means to provide a carry-out signal in response to a predetermined logical operation; the apparatus being characterized in that the selective gating means of each cell is provided by a single 2-to-l multiplexer, or its logical equivalent, and in that all N cells are alike.

Claim 11

An apparatus for adding first and second binary operands, each -aving a nominal length of N bits and a carry-in signal, and for providing a sum output signal having N bits and a carry-out signal, said apparatus comprising: N logic cells each for receiving a corresponding bit of each operand and providing a sum output signal, and a carry-out signal, each cell of the apparatus comprising first logic means comprising first and second gate means (231,241,232,242,233,243,234,244), each of which has a first input for receiving a corresponding bit signal of the first operand (Ao-A3) and a second input for receiving a corresponding bit signal of the second operand (B O -B 3 ), to provide first and second output signals respectively in response to a predetermined logical operation; selective gating means (210,211,212,213) having a first, control, input for receiving the second output signal from the second gate means, a second signal input for receiving the first output signal from the first gate means, and a third signal input for receiving the carry-in signal, for providing the carry-out signal in response to a predetermined logical operation; and second logic means (245,246,247,248) having a first input for receiving the carry-in signal, and a second input for receiving the second output signal of the second gate means to provide a carry-out signal in response to a predetermined logical operation; the apparatus being characterized in that the selective gating means of each cell is provided by a single 2-to-l multiplexer, or its logical equivalent, and in that all N cells are alike.