Digital data code conversion circuit for variable-word-length data code

Claim 2

A digital data code conversion circuit for a variable-word-length data code, comprising: a data code conversion portion (4)'for converting variable-word-length data codes having a word-length less than or equal to a predetermined number n into fixed-word-. length data codes having a word-length equal to the predetermined number n by dividing and combining the input variable-word-length data codes according to word-length information for said input variable-word-length data codes; and a preparation circuit (3) arranged in a stage preceding the data code conversion portion (4), the preparation circuit (3) dividing an input variable word length data code having a word-length greater than the predetermined number n into a plurality of variable-word-length data codes each having a word-length less than or equal to the predetermined number n and producing word-length information for the plurality of variable-word-length data codes, wherein the data code conversion portion (3) is operated at an operation rate proportional to the data input rate multiplied by the number of divisions of the variable-word-length data codes.

Claim 3

A digital data code conversion circuit for a variable-word-length data code according to claim 1, wherein the data code conversion portion (4)comprises: a data-shift circuit (41) for receiving the divided variable-word-length data code from the preparation circuit (3) and shifting the bit position of the received variable-word-length data code; a selector circuit (43,44) for receiving the data output from the data-shift circuit (41); first (42) and second (45) register circuits, the first register circuit (42) receiving the data output from the data-shift circuit (41), the selector circuit (43, 44) also receiving the data output from the first register circuit (42) and the data output from the second register circuit (45), and the second register circuit (45) receiving the data output from the selector circuit (43, 44); and a control circuit (47) for receiving the word-length information from the preparation circuit (3) the control circuit (47) controlling the data-shift circuit (41) so as to shift the received variable-word-length data code <DI 1 ' to DI nl ') by a bit number determined in accordance with the word-length information and cones trolling the selector circuit (43, 44) so that the selector circuit (43, 44) outputs the combined data of the data output from the second register circuit (45) and of the data output from the data-shift circuit (41) when the data output from the second register circuit (45) is not fixed-word-length data having a word length of n bits and so that the selector circuit (43, 44) outputs the combined data of the data output from the first register circuit (42) and of the data output from the data-shift circuit (41) when the data output from the second register circuit (45) is fixed-word-length data having a word length of n bits.