EP0098111A2 — Vertical IGFET device and method for fabricating …

Claim 1

Independent Claim 193 words

A method for fabricating a vertical IGFET device, comprising the steps of: providing a substrate (10) having a monocrystalline semiconductor portion of a first conductivity type at a surface (12) thereof; forming a first insulating layer (14) on . said surface (12); forming a gate electrode (20) of predetermined thickness on the first insulating layer (14), the electrode (20) having an aperture (22) therethrough, said aperture (22) overlying a portion of said monocrystalline semiconductor portion; and coating the apertured electrode with a second insulating layer (24) so as to form an insulated gate (26);characterized in that: the first insulating layer (14) is etched, using the insulated gate (26) as an etch mask, so as to expose an area (30) of monocrystalline semiconductor material within the aperture (28) of the insulated gate (26); semiconductor material (32) is epitaxially grown from said area (30) of monocrystalline semiconductor material so as to substantially fill the aperture (28); and said epitaxial semiconductor material (32) is doped so as to form a region (34) of second conductivity type disposed substantially opposite said gate electrode (20), and a region (36) of first conductivity type overlying said second-conductivity-type region (34).

Claim 2

Independent Claim 193 words

A method for fabricating a vertical IGFET device, comprising the steps of: providing a substrate (10) having a monocrystalline semiconductor portion of a first conductivity type at a surface (12) thereof; forming a first insulating layer (14) on . said surface (12); forming a gate electrode (20) of predetermined thickness on the first insulating layer (14), the electrode (20) having an aperture (22) therethrough, said aperture (22) overlying a portion of said monocrystalline semiconductor portion; and coating the apertured electrode with a second insulating layer (24) so as to form an insulated gate (26);characterized in that: the first insulating layer (14) is etched, using the insulated gate (26) as an etch mask, so as to expose an area (30) of monocrystalline semiconductor material within the aperture (28) of the insulated gate (26); semiconductor material (32) is epitaxially grown from said area (30) of monocrystalline semiconductor material so as to substantially fill the aperture (28); and said epitaxial semiconductor material (32) is doped so as to form a region (34) of second conductivity type disposed substantially opposite said gate electrode (20), and a region (36) of first conductivity type overlying said second-conductivity-type region (34).

Claim 3

Dependent Claim 30 words

A method in accordance with Claim 1, wherein said first insulating layer comprises: a lower layer disposed on said substrate surface; and an upper layer disposed on said lower layer.

Claim 4

Dependent Claim 21 words

A method in accordance with Claim 2, wherein said lower layer is silicon dioxide and said upper layer is silicon nitride.

Claim 5

Dependent Claim 29 words

A method in accordance with Claim 1, wherein said gate electrode is formed by the steps of: forming a layer of doped polycrystalline silicon; and photolithographically defining said aperture.

Claim 6

Dependent Claim 50 words

A method in accordance with Claim 1, wherein said gate electrode is formed by the steps of: forming a layer of doped polycrystalline silicon; forming a supplementary insulating layer on the surface of said polycrystalline silicon; and forming an aperture through said supplementary insulating layer and said polycrystalline silicon layer.

Claim 7

Dependent Claim 52 words

A method in accordance with Claim 1, wherein said second insulating layer is silicon dioxide and further comprising: providing a doped polycrystalline silicon gate electrode; and forming said second insulating layer by thermal oxidation so as to yield a predetermined thickness of said second insulating layer within said aperture in said electrode.

Claim 8

Dependent Claim 27 words

A method in accordance with Claim 1, further comprising: between said etching and said growing steps, doping said area of monocrystalline semiconductor material exposed within said aperture.

Claim 9

Dependent Claim 25 words

.8. A method in accordance with Claim 7 comprising ion implanting a conductivity modifier of the first conductivity type so as to achieve said doping.

Claim 10

Dependent Claim 19 words

A method in accordance with Claim 1, further comprising doping said epitaxial semiconductor material simultaneous with the growing thereof.

Claim 11

Dependent Claim 33 words

A method in accordance with Claim 1, wherein said substrate comprises an insulating wafer having a layer disposed on a surface thereof, said layer comprising a monocrystalline semiconductor island surrounded by insulating material.

Claim 12

Dependent Claim 46 words

11 . A method in accordance with Claim 10, wherein said substrate is formed by the steps of: forming a monocrystalline silicon layer on an insulating wafer; masking a portion of said silicon layer; oxidizing the unmasked portion of said silicon layer; and stripping said mask.

Claim 13

Dependent Claim 119 words

A vertical IGFET device, comprising: a substrate (10) having a monocrystalline semiconductor portion of a first conductivity type at a surface (12) thereof; and an insulated gate (26) disposed on the surface (12) of said substrate (10); characterized in that: said insulated gate (26) includes an aperture (28) to an area (30) of the monocrystalline semiconductor portion; and an epitaxial semiconductor region (32) extends from the surface (12) of said substrate (10) within said aperture (28) to a height substantially equal to that of the insulated gate (26), said epitaxial region (32) having a portion (34) of second conductivity type within said aperture (28), and a portion (36) of first conductivity type overlying the second conductivity type portion (34).

Claim 14

Dependent Claim 119 words

A vertical IGFET device, comprising: a substrate (10) having a monocrystalline semiconductor portion of a first conductivity type at a surface (12) thereof; and an insulated gate (26) disposed on the surface (12) of said substrate (10); characterized in that: said insulated gate (26) includes an aperture (28) to an area (30) of the monocrystalline semiconductor portion; and an epitaxial semiconductor region (32) extends from the surface (12) of said substrate (10) within said aperture (28) to a height substantially equal to that of the insulated gate (26), said epitaxial region (32) having a portion (34) of second conductivity type within said aperture (28), and a portion (36) of first conductivity type overlying the second conductivity type portion (34).

Claim 15

Dependent Claim 50 words

A device in accordance with Claim 12, wherein said substrate (10) comprises monocrystalline silicon; and said insulated gate (26) comprises a layer of doped, polycrystalline silicon having a plurality of apertures (28) therein, each aperture (28) including an epitaxial region (32) extending from the surface (12) of said substrate (10).

Claim 16

Dependent Claim 67 words

A device in accordance with Claim 13, wherein said substrate (10) comprises a plurality of said monocrystalline semiconductor portions at a surface thereof and wherein said insulated gate (26) comprises a layer of doped, polycrystalline silicon having a plurality of apertures (28) therein, each aperture (28) exposing a monocrystalline semiconductor area (30) and including an epitaxial region (32) extending from the surface (12) of said substrate (10).

Claim 17

Dependent Claim 116 words

An integrated device (110) incorporating a plurality of interconnected vertical IGFETs on a surface (114) of a substrate (112), comprising: a monocrystalline semiconductor region (126) extending from an area of the surface (114) of said substrate (112)tcharacterized in that: a plurality of insulated gates (116, 134, 136 and 138), which can be selectively biased, aree disposed on the surface (114) of said substrate (112), each of said insulated gates (116, 134, 136 and 138) being contiguous with a segment of the monocrystalline semiconductor region (126) such that a predetermined voltage applied to a particular insulated gate (116, 134, 136 and 138) creates an inversion channel in the segment of th monocrystalline semiconductor region (126) contiguous therewith.

Claim 18

Dependent Claim 116 words

An integrated device (110) incorporating a plurality of interconnected vertical IGFETs on a surface (114) of a substrate (112), comprising: a monocrystalline semiconductor region (126) extending from an area of the surface (114) of said substrate (112)tcharacterized in that: a plurality of insulated gates (116, 134, 136 and 138), which can be selectively biased, aree disposed on the surface (114) of said substrate (112), each of said insulated gates (116, 134, 136 and 138) being contiguous with a segment of the monocrystalline semiconductor region (126) such that a predetermined voltage applied to a particular insulated gate (116, 134, 136 and 138) creates an inversion channel in the segment of th monocrystalline semiconductor region (126) contiguous therewith.

Claim 19

Independent Claim 23 words

A device (110) in accordance with Claiml5 wherein each of the inversion channels is perpendicular to the surface (114) of said substrate (112).

Claim 20

Dependent Claim 17 words

A device (110) in accordance with Claim 16 wherein the segments are disposed in an overlying relationship.

Claim 21

Independent Claim 35 words

A device (110) in accordance with Claim IS wherein each insulated gate (116, 134, 136 and 1 3 8) comprises an electrode having an aperture (122) therein, said electrode being substantially surrounded by insulation (120).

Claim 22

Dependent Claim 35 words

A device (110) in accordance with Claim 18 wherein the apertures (122) in the insulated gates (116, 134, 136 and 138) are coincident and said monocrystalline semiconductor region (126) extends through the coincident apertures (122).

Claim 23

Independent Claim 38 words

A device (110) in accordance with Claim l& wherein the monocrystalline semiconductor region comprises overlying source, body and drain regions (128, 130 and 132) of alternate conductivity type, each body region (130) being disposed substantially opposite an electrode.

Claim 24

Dependent Claim 79 words

A device (110) in accordance with Claim 15, wherein the monocrystalline semiconductor region (126) is . substantially relatively low conductivity material of opposite conductivity type to a monocrystalline contact portion (113) of relatively high conductivity from which the monocrystalline semiconductor region (126) extends and includes a drain region (140), also of relatively high conductivity, which is of similar conductivity type as said contact portion (113), said drain region (140) comprising the uppermost portion of the monocrystalline semiconductor region (126).

Claim 25

Dependent Claim 18 words

A device in (150) in accordance with Claim 15 wherein said segments are laterally displaced from each other.

Claim 26

Dependent Claim 32 words

A device (150) in accordance with Claim 22 wherein each insulated gate (158) comprises a finger having an end, said segments of the monocrystalline semiconductor region (166) being contiguous with said ends.

Claim 27

Dependent Claim 27 words

24 A device (150) in accordance with Claim 23 wherein each of said insulated gates (158) comprises an electrode (160) which is substantially surrounded by insulation (162).

Claim 28

Dependent Claim 42 words

. A device (150) in accordance with Claim 23 wherein said insulated gates (158) are disposed in a radial configuration on the surface (154) of said substrate (152) and the monocrystalline semiconductor region (166) extends from the center of the radial configuration.

Claim 29

Dependent Claim 42 words

A device (150) in accordance with Claim 23, wherein said monocrystalline semiconductor region (166) includes source, body and drain regions (170,168 and 172) of alternate conductivity type and the body region (168) is disposed substantially opposite the plurality of gate electrodes (160).

Claim 30

Dependent Claim 33 words

A device (110 or 150) in accordance with Claim 20 or 26, wherein the substrate (112 or 152) is monocrystalline silicon of the same conductivity type as the source region (128 or 170).

Claim 31

Dependent Claim 46 words

A device (110 or 150) in accordance with Claim 15 or 23, wherein the surface (114 or 154) of said substrate (112 or 152) includes a monocrystalline contact portion (113 or 156), of relatively high conductivity, from which the monocrystalline semiconductor region (126 or 166) extends.

Claim 32

Dependent Claim 35 words

A device (110 or 150) in accordance with Claim 15 or 23, wherein the uppermost portion (114 or 172) of the monocrystalline semiconductor region (126 or 166) is connected to a source of drain voltage.

Claim 33

Dependent Claim 42 words

A device (110 or 150) in accordance with Claim 15 or 23 wherein the area (113 or 156) of the substrate (112 or 152) from which the monocrystalline semiconductor region (126 or 166) extends is connected to a source of source voltage.

Claim 34

Dependent Claim 135 words

An integrated circuit device (210) incorporating a plurality of interconnected vertical IFGETs on a substrate, comprising: an insulated gate (222) disposed on a surface (214) of the substrate (212); characterised in that first and second monocrystalline semiconductor regions (236 and 238) extend, respectively, from first and second monocrystalline substrate portions (220 and 218) at the surface (214) of said substrate (212), said monocrystalline semiconductor regions (236 and 238) each being contiguous with a part of the insulated gate (222); and the first monocrystalline semiconductor region (236) has a body region (242) of first conductivity type, and the second monocrystalline semiconductor region(238) has a body region (248) of second conductivity type, such that a predetermined voltage applied to the insulated gate (222) selectively creates an inversion channel in one of the body regions (242 or 248).

Claim 35

Dependent Claim 135 words

An integrated circuit device (210) incorporating a plurality of interconnected vertical IFGETs on a substrate, comprising: an insulated gate (222) disposed on a surface (214) of the substrate (212); characterised in that first and second monocrystalline semiconductor regions (236 and 238) extend, respectively, from first and second monocrystalline substrate portions (220 and 218) at the surface (214) of said substrate (212), said monocrystalline semiconductor regions (236 and 238) each being contiguous with a part of the insulated gate (222); and the first monocrystalline semiconductor region (236) has a body region (242) of first conductivity type, and the second monocrystalline semiconductor region(238) has a body region (248) of second conductivity type, such that a predetermined voltage applied to the insulated gate (222) selectively creates an inversion channel in one of the body regions (242 or 248).

Claim 36

Dependent Claim 57 words

32 A device (210) in accordance with Claim 31 , wherein: the substrate (212) is bulk, monocrystalline silicon; the first monocrystalline substrate portion (220) is of second conductivity type; the second monocrystalline substrate portion (218) is of first conductivity type; and said first and second monocrystalline substrate portions (220 and 218) are electrically isolated from each other.

Claim 37

Dependent Claim 59 words

A device (400) in accordance with Claim 31, wherein the substrate (402) comprises: an insulating wafer (402) having a major surface (404) from which the first and second monocrystalline substrate portions extend, said monocrystalline substrate portions being separated from each other by an isolation oxide (410) which is disposed on the major surface (404) of said insulating wafer (402).

Claim 38

Dependent Claim 32 words

3 4 . A device (210) in accordance with Claim 31 , wherein the insulated gate (222) comprises: an electrode (224) of doped polycrystalline silicon which is substantially surrounded by insulation (226).

Claim 39

Dependent Claim 93 words

3 5. A device (210) in accordance with Claim 31, wherein: a field insulation (232) surrounds the insulated gate (222) on the surface (214) of the substrate (212), the field insulation (232) being spaced from the insulated gate (222) so as to define a pair of apertures (234) to the surface (214) of said substrate (212), the apertures (234) being disposed over the first and second monocrystalline substrate portions (220 and 218) and the monocrystalline semiconductor regions (236 and 238) extending from the surface (214) of said substrate (212) within the apertures (234).

Claim 40

Dependent Claim 43 words

A device (210) in accordance with Claim 31, wherein: the insulated gate (222) includes first and second apertures (230 and 234) therein, said first and second monocrystalline semiconductor regions (236 and 238) extending from the substrate (212) within said apertures (230 and 234).

Claim 41

Dependent Claim 69 words

A device (210) in accordance with Claim 31., wherein each monocrystalline semiconductor region (236, 238) comprises: a source/drain region (240 , 246) underlying the body region (242, 248) and a source/drain region (244, 250) overlying the body region (242, 248), said source/drain regions (240, 244, 246 and 250) being of opposite conductivity type to the body region (242, 248) and of higher conductivity than the body region (242, 248).

Claim 42

Dependent Claim 94 words

38 . A device in accordance with Claim 37, further comprising: means for connecting a source of predetermined voltage (V DD ) to the underlying source/drain region (240) of the second monocrystalline semiconductor region (238); means for connecting a source of relatively low-level voltage (V SS ) to the underlying source/drain region of the first monocrystalline semiconductor region (238); an input terminal (IN) connected to the insulated gate (222); and an output terminal (OUT) connected to the overlying source/drain regions (244, 250) of both the first and second monocrystalline semiconductor regions (236 and 238).

Claim 43

Dependent Claim 115 words

A device (400) in accordance with Claim 31, further comprising: a second insulated gate (416) disposed on the surface (412) of said substrate (402), the second insulated gate (416) being contiguous with the body region (418) of the first monocrystalline semiconductor region and the body region (420) of the second monocrystalline semiconductor region; a source/drain region (406, 408) underlying each body region (418, 420) and of opposite conductivity type thereto; and first and second source/drain regions (422, 424, 428, 430) overlying each body region (418, 420), said first and second overlying source/drain regions (422, 424, 428, 430) being isolated from each other and being of opposite conductivity type to the body region (418, 420) thereunder.

Claim 44

Dependent Claim 140 words

40 . A device (400) in accordance with Claim 39, further comprising: means for connecting a source of predetermined voltage (V DD ) to the underlying source/drain region (408) of first conductivity type; 1 means for connecting a source of relatively lower voltage (V SS ) to the underlying source/drain region (406) of second conductivity type; an input/output terminal (B), which connects the first source/drain region (428) which overlies the second conductivity type body region (420) to the first source/drain region (422) which overlies the first conductivity type body region (418) to the first insulated gate (414); and a second input/output terminal (B), which connects the second source/drain region (430) which overlies the second conductivity type body region (420) to the second source/drain region (424) which overlies the first conductivity type body region (418) to the second insulated gate (416).

Claim 45

Independent Claim 151 words

A device (500) in accordance with Claim39 , further comprising: means for connecting a source of predetermined voltage (V DD ) to the underlying source/drain region of first conductivity type; means for connecting a source of relatively lower voltage (V SS ) to the underlying source/drain region of second conductivity type; means for connecting the first source/drain region which overlies the second conductivity type body region to the first source/drain region (422) which overlies the first conductivity type body region to the first insulated gate electrode (414); means for connecting the second source/ drain region which overlies the second conductivity type body region to the second source/drain region (424) which overlies the first conductivity type body region to the second insulated gate electrode (416); and first and second access transistors (502 and 504) disposed, respectively, on the first and second source/drain regions (422 and 424) which overlie a particular body region.

Claim 46

Dependent Claim 31 words

A device (500) in accordance with Claim 39, wherein: the first and second access transistors (502 and 504) are vertical IGFETs and are controlled by a common insulated gate electrode (506).

Claim 47

Dependent Claim 48 words

A device (500) in accordance with Claim 42, wherein: the first and second source/drain regions (422 and 424) which overlie a particular body region are isolated from each other by an isolation layer (426); and said common insulated gate electrode (506) is disposed on said isolation layer (426).

Vertical IGFET device and method for fabricating same

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