Semiconductor memory device with redundancy decoder circuit

Claim 2

A semiconductor memory device comprising a memory cell array_including a plurality of memory cells (14); a decoder circuit (13) which accesses a specified one of the memory cells (14) in accordance with an address input; a redundancy memory cell (15) which is to replace a defective memory cell contained in the memory cell array; and a redundancy circuit (11) which receives the address input and is operative to produce a selection signal for selecting the redundancy memory cell when the received address input specifies the address corresponding to the defective memory cell; characterised in that the redundancy decoder circuit (11) includes a plurality of depletion-type FAMOS transistors (41 -44) each of which contains a floating gate (FG) and a control gate (CG), whereby -in a write operation mode a write operation can be performed in selected ones of the FAMOS transistors at respective floating gates in a pattern, as a whole, identical to the pattern of the address input so as to enable the selection signal to be produced in a normal memory access mode.

Claim 3

A semiconductor memory device according to claim 1, wherein a predetermined voltage, for applying to the control gate of each FAMOS transistor during a mode other than the write operation mode, is set to be ground level or lower.

Claim 4

A semiconductor memory device according to claim 1 or claim 2, wherein the depletion-type FAMOS transistors (41-44) are commonly connected at their drains and also at their control gates and are connected at their sources in series with respective gate transistors (31-34), at their one side electrodes, while the other side electrodes of the gate transistors are grounded, the gate-electrodes of the gate transistors being arranged to receive the address input so as to make some of the gate transistors conductive and others nonconductive in accordance with the address input.

Claim 5

A semiconductor memory device according to claim 3, wherein the commonly connected drains of the depletion type FAMOS transistors (41-44) receive a write voltage (V ) during the write operation mode, and a power source voltage (V ) during the normal memory access mode at which time the control gates of the depletion type FAMOS transistors receive a voltage having a ground level or lower.

Claim 6

A semiconductor memory device according to claim 4, wherein the write voltage (V pp ) and the power source voltage (V ) are selectively applied to the commonly connected drains of the depletion type FAMOS transistors (41-44) via a transistor pair (25, 26), one (25) of which is connected to a write voltage source, and the other (26) of which is connected to a power source.

Claim 7

A semiconductor memory device comprising a memory cell array including a pluraltiy of memory cells (14); a decoder circuit (13) which accesses a specified one of the memory cells (14) in accordance with an address input; a redundancy cell (15) which is to replace a defective memory cell contained in the memory cell array; and a redundancy decoder circuit (11) which receives the address input and is operative to produce a selection signal for selecting the redundancy memory cell when the received address input specifies the address corresponding to the defective memory cell; characterised in that the redundancy decoder circuit includes a plurality of FAMOS transistors (41-44), each of which contains a floating gate and a control gate, and a write operation is performed in each of a selected one or more FAMOS transistors at respective floating gates in a pattern, as;a whole, identical to the pattern of the address input so as to produce the selection signal, each of the FAMOS transistors is made as a depletion type and a predetermined voltage is applied to the control gate of each said depletion-type FAMOS transistors.

Claim 8

A semiconductor memory device comprising a memory cell array including a pluraltiy of memory cells (14); a decoder circuit (13) which accesses a specified one of the memory cells (14) in accordance with an address input; a redundancy cell (15) which is to replace a defective memory cell contained in the memory cell array; and a redundancy decoder circuit (11) which receives the address input and is operative to produce a selection signal for selecting the redundancy memory cell when the received address input specifies the address corresponding to the defective memory cell; characterised in that the redundancy decoder circuit includes a plurality of FAMOS transistors (41-44), each of which contains a floating gate and a control gate, and a write operation is performed in each of a selected one or more FAMOS transistors at respective floating gates in a pattern, as;a whole, identical to the pattern of the address input so as to produce the selection signal, each of the FAMOS transistors is made as a depletion type and a predetermined voltage is applied to the control gate of each said depletion-type FAMOS transistors.