EP0097499A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Access request control apparatus for a data processing system
Assignee: Fujitsu Ltd
•
Filing: 1983-06-17
•
Granted: —
•
Expires: 2003-06-17
Abstract
Abstract In access request control apparatus, more specifically apparatus for determining priority between a plurality of access requests in memory control apparatus, one access request from amongst a plurality of requests from channel processing devices (CHP) is seiected by a first priority determination circuit, whilst from amongst the selected CHP access request, acces requests from a plurality of central processing units and loop back access requests from a pipeline control circuit, one request is selected by a second priority determination circuit. If a CHP access request is not selected by the second priority determination circuit, or is selected but nullified in the course of pipeline operations, the request is returned again to the first priority determination circuit. A higher priority is given to the request when it is returned to the first priority determination circuit. In addition, the priority algorithm of the second priority determination circuit takes into account the different kinds of operations involved in processing different access requests and thereby highly efficient memory access can be realized.
Inventors
- 👤 Masanori Takahashi
- 👤 Hidehiko Fujitsu Ltd. Patent Dpt. Nishida
- 👤 Minoru Koshino
- 👤 Akira Hattori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:05
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
154 words
Access request control apparatus, for controlling access to memory apparatus by a plurality of access requesting apparatuses such as channel processing units and central processing units forming a data processing system wherein; means are provided which are operable to determine priority as between a plurality of access requests simultaneously accepted from the plurality of access requesting apparatuses, to assign priority values, to select only one such access request to start processing of the selected request, and to redetermine priority if processing is diabled before completion by nullifying the priority of the selected access request and by returning it to its initial condition, namely to its condition when it was accepted, and which means are further operable to allow such access request which has once been so nullified to take part again in priority determination and for that purpose to assign a higher priority value to such access request for competition with other access requests.
Claim 2
Dependent Claim
154 words
Access request control apparatus, for controlling access to memory apparatus by a plurality of access requesting apparatuses such as channel processing units and central processing units forming a data processing system wherein; means are provided which are operable to determine priority as between a plurality of access requests simultaneously accepted from the plurality of access requesting apparatuses, to assign priority values, to select only one such access request to start processing of the selected request, and to redetermine priority if processing is diabled before completion by nullifying the priority of the selected access request and by returning it to its initial condition, namely to its condition when it was accepted, and which means are further operable to allow such access request which has once been so nullified to take part again in priority determination and for that purpose to assign a higher priority value to such access request for competition with other access requests.
Claim 3
Dependent Claim
181 words
1 Apparatus as claimed in claim 1, employing a pipeline control system, comprising a first priority determination circuit operable to select one CHP access request from two or more competing CHP access requests, and a second priority determination circuit which, when two or more access requests, such as a selected CHP access request, access requests from the plurality of CPU's and loop back access requests for using the pipeline again, compete, in general gives:- as between CPU access requests, higher priority to one request in accordance with a flag bit indicating priority as between CPU access requests; as between the selected CHP access request and CPU access requests, higher priority to the selected CHP access request; and as between a loop back access request and CHP and CPU access requests, higher priority to the loop back access request; and wherein if the CHP access request selected by the first priority determination circuit is not selected by the second priority determination circuit, a higher priority is given to said CHP access request for subsequent priority determination in the first priority determination circuit.
Claim 4
Dependent Claim
37 words
Apparatus as claimed in claim 2, wherein the first priority determination circuit includes respective state indication registers which indicate the states of the CHP's and is operable to determine priority based on the contents of such registers.
Claim 5
Dependent Claim
197 words
Access request control apparatus, for controlling access to a memory apparatus by a plurality of access requesting apparatuses such as the channel processing units and central processing units forming a data processing systemiwherein priority determination circuitry is provided, which operatesin accordance with a theoretical priority determination structure having:- a first stage which selects one CHP access request from amongst two or more competing CHP access requests, and a second stage in which when two or more access requests, such as the selected CHP access request, CPU.access requests, and loop back access requests for using the pipeline again, compete, gives, as a rule:- as between CPU access requests, higher priority to one request in accordance with a flag bit indicating priority as between CPU access requests; as between the selected CHP access request and CPU access requests, higher priority to the selected CHP access request; and as between a loop back access request and CHP and CPU access requests, higher priority to the loop back access request ; and wherein, in priority determination in the second stage, priority is modified in accordance with the kinds of operation signified by the access requests, and thereafter priority is finally determined.
Claim 6
Dependent Claim
197 words
Access request control apparatus, for controlling access to a memory apparatus by a plurality of access requesting apparatuses such as the channel processing units and central processing units forming a data processing systemiwherein priority determination circuitry is provided, which operatesin accordance with a theoretical priority determination structure having:- a first stage which selects one CHP access request from amongst two or more competing CHP access requests, and a second stage in which when two or more access requests, such as the selected CHP access request, CPU.access requests, and loop back access requests for using the pipeline again, compete, gives, as a rule:- as between CPU access requests, higher priority to one request in accordance with a flag bit indicating priority as between CPU access requests; as between the selected CHP access request and CPU access requests, higher priority to the selected CHP access request; and as between a loop back access request and CHP and CPU access requests, higher priority to the loop back access request ; and wherein, in priority determination in the second stage, priority is modified in accordance with the kinds of operation signified by the access requests, and thereafter priority is finally determined.
Claim 7
Dependent Claim
94 words
Apparatus as claimed in claim 4, wherein CPU access requests include an access request involving access of a unit of n bytes, and include a block access request where such an n-byte access has to be effected continuously m times.(n, m are integers larger than 1), and wherein, in the second priority determination stage, a higher priority is given to the second and successive such n-byte access requests of a block access request than is given to the first n-byte access request of a block access request or to a single n-byte access request.
Claim 8
Dependent Claim
63 words
Apparatus as claimed in claim 5, wherein block access flags are provided in correspondence to the respective CPU's in the second priority determination stage, and when the first n-byte access request of a block access request is selected, the block access flag of the relevant CPU is turned ON indicating that the access request has higher priority than access requests of other CPU's.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.