Lateral bi-directional notch fet

Claim 2

A bidirectional FET (102, Figure 13), comprising: a first source region (140) of one conductivity type semiconductor material; a first channel region (144) of opposite conductivity type semiconductor material forming a junction (113) with said first source region (140); a drift region (148) of one conductivity type semiconductor material forming another junction (158) with said first channel region (144); a second channel region (146) of said opposite conductivity type semiconductor material forming a junction (154) with said drift region (148); a second source region (142) of said one conductivity type semiconductor material forming a junction (143) with said second channel region (146); a notch (118) extending between and separating said first and second source regions (140 and 142) and said first and second channel regions (144 and 146), and extending into said drift region (148); insulated gate means (132) in said notch (118) proximate said first and second channel regions (144 and 146) and adapted for application of an electrical potential for producing electric fields of sufficient intensity to invert the the conductivity type in said first and second channel regions (144 and 146); whereby upon application of voltage of either polarity to said first and second source regions (140 and 142), electric current can flow in a respective corresponding direction between them, under control of said electrical potential of said gate means (132), the conductive current path through said drift region (148) traversing along one side of said notch (118) then around the end thereof then along the other side of said notch (118).

Claim 3

The invention according to Claim 1 wherein said channel regions (144 and 146) are laterally spaced by said notch (118), and said notch (118) extends downwardly from a top major surface (106) of said FET (102), said channel regions (144 and 146) extending generally vertically along respective sides of said notch (118), said drift region (148) being below said channel regions (144 and 146).

Claim 4

The invention according to Claim 2 wherein said source regions (140 and 142) are laterally spaced along said top major surface (106) by said notch (118) therebetween, said source regions (140 and 142) being above respective said channel regions (144 and 146).

Claim 5

The invention according to Claim 3 comprising a pair of main electrodes (150 and 152) each connected to a respective said source region (140 and 142), and wherein said insulated gate means (132) comprises insulation layer means (124) extending along the inner surface of said notch (118), and gate electrode means (132) disposed in said notch (118) along said insulation layer means (124) such that said gate electrode means (132) extends in close proximity along and insulated from said vertical channel regions (144 and 146).

Claim 6

The invention according to Claim 4 wherein said FET (102) has an OFF state in the absence of said electric gate potential, with the junction (158) between said drift region (148) and one of said channel regions (144) blocking current flow toward one of said main electrodes (150), and with the junction (154) between said drift region (148) and the other of said channel regions (146) blocking current flow toward the other of said main electrodes (152).

Claim 7

The invention according to Claim 5 wherein the drift region current path between said main electrodes (150 and 152) extends from said source regions (140 and 142) downwardly through said channel regions (144 and 146) and downwardly and around the bottom of said notch (118) so as to increase the drift region current path length and afford higher OFF state blocking voltage capability, without increasing the lateral dimension along said top major surface (106), whereby to afford a high density, high voltage bidirectional FET structure (102).

Claim 8

The invention according to Claim 6 wherein said notch (118 or 268, Figure 21) extends downwardly into said drift region (258) a substantial distance below said gate electrode means (238) to substantially diminish attraction of carriers by said gate electrode means (238) from said drift region (258) toward the edges of said notch (268), to prevent unwanted inducement of conduction channels in said OFF state and afford higher OFF state voltage blocking capability.

Claim 9

The invention according to Claim 7 wherein said notch (268) extends downwardly into said drift region (258) to a depth substantially below said channel regions (254 and 262), and said gate electrode means (238) extends downwardly to about the depth of said junctions (260 and 264) between said channel regions (254 and 262) and said drift region (258).

Claim 10

The invention according to Claim 6 wherein said gate electrode means (132, Figure 13) is referencable to a common potential level with one of said main electrodes (150 or 152) in said OFF state of said FET while still maintaining said increased voltage blocking capability.

Claim 11

The invention according to Claim 8 wherein said gate electrode means (238) comprises titanium discilicide.

Claim 12

The invention according to Claim 8 wherein said gate electrode means (238) comprises tantalum disilicide.

Claim 13

The invention according to Claim 8 wherein said gate electrode means (238) comprises tungsten disilicide.

Claim 14

The invention according to Claim 8 wherein the portion (228) of said notch (268) below said gate electrode means (238) comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

Claim 15

The invention according to Claim 6 wherein said notch (268) is anisotropically etched and oxidized.

Claim 16

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material of one conductivity type having a top major surface (106); a pair of channel regions (144 and 146) of the other conductivity type laterally spaced in said substrate (104); a pair of source regions (140 and 142) of said one conductivity type laterally spaced along said top major surface (106) and each forming a junction (113 and 143) with a respective one of said channel regions (144 and 146); a notch (118) in said substrate (104) extending downwardly from said top major surface (106) between said source regions (140 and 142) and said channel regions (144 and 146) into a drift region (148) in said substrate (104), such that the conductive current path is directed from one source region (140) downwardly through a generally vertical one said channel region (144) along one side of said notch (118), then further downwardly into said drift region (148) along said one side of said notch (118), then around the bottom of said notch (118), then upwardly along the other side of said notch (118) in said drift region (148), then upwardly along a generally vertical other said channel region (146) to said other source region (142), with the same path conducting current in the reverse direction from said other source region (142) to said one source region (140); a pair of main electrodes (150 and 152) connected respectively to said source regions (140 and 142); and insulated gate electrode means (132) in said notch (118) including portions proximate said generally vertical channel regions (144 and 146) for attracting given polarity carriers to invert said channel regions (144 and 146) to said one conductivity type in response to given gate potential, such that current may flow in either direction between said main electrodes (150 and 152).

Claim 17

A bidirectional lateral power FET (102), comprising: a substrate (104) of semiconductor material of one conductivity type having a top major surface (106); a pair of channel regions (144 and 146) of the other conductivity type laterally spaced in said substrate (104); a pair of source regions (140 and 142) of said one conductivity type laterally spaced along said top major surface (106) and each forming a junction (113 and 143) with a respective one of said channel regions (144 and 146); a notch (118) in said substrate (104) extending downwardly from said top major surface (106) between said source regions (140 and 142) and said channel regions (144 and 146) into a drift region (148) in said substrate (104), such that the conductive current path is directed from one source region (140) downwardly through a generally vertical one said channel region (144) along one side of said notch (118), then further downwardly into said drift region (148) along said one side of said notch (118), then around the bottom of said notch (118), then upwardly along the other side of said notch (118) in said drift region (148), then upwardly along a generally vertical other said channel region (146) to said other source region (142), with the same path conducting current in the reverse direction from said other source region (142) to said one source region (140); a pair of main electrodes (150 and 152) connected respectively to said source regions (140 and 142); and insulated gate electrode means (132) in said notch (118) including portions proximate said generally vertical channel regions (144 and 146) for attracting given polarity carriers to invert said channel regions (144 and 146) to said one conductivity type in response to given gate potential, such that current may flow in either direction between said main electrodes (150 and 152).

Claim 18

The invention according to Claim 15 wherein said substrate (104) has a first top layer (110) formed therein, followed by formation of a second top layer (112) in said first top layer (110), followed by formation of said notch (118) through said second top layer (112) and through said first top layer (110) into said drift region portion (148) of said substrate (104) therebelow, said notch (118) dividing said first top layer (110) into said first and second channel regions (144 and 146) on opposite sides thereof, said notch (118) dividing said second top layer (112) into said first and second source regions (140 and 142) on opposite sides thereof.

Claim 19

The invention according to Claim 16 comprising a plurality of laterally spaced second said top layers (112, 114, 116) formed in said first top layer (110), and comprising a plurality of notches (118, 120, 122) extending downwardly from said top major surface (106) through a respective one of said second top layers (112, 114, 116) and then through said first top layer (110) and into said drift region (148) of said substrate (104) therebelow, whereby to afford an integrated structure having a plurality of said FETs.

Claim 20

The invention according to Claim 17 wherein said notches (278, 268, 276, Figure 21) extend downwardly into said drift region (258) a substantial distance below said gate electrode means (238) to substantially diminish attraction of carriers by said gate electrode means (238) from said drift region (258) toward the edges of said notch (268), to prevent unwanted inducement of conduction channels in an OFF state of said FET and afford higher OFF state voltage blocking capability.

Claim 21

The invention according to Claim 18 whereinsaid notch (268) extends downwardly into said drift region (258) to a depth substantially below said channel regions (254 and 262), and said gate electrode means (238) extends downwardly to about the depth of said channel regions (254 and 262).

Claim 22

The invention according to Claim 19 wherein the portion (228) of said notch (268) below said gate electrode means (238) comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

Claim 23

The invention according to Claim 20 wherein said gate electrode means (238) comprises titanium disilicide.

Claim 24

The invention according to Claim 20 wherein said gate electrode means (238) comprises tantalum disilicide.

Claim 25

The invention according to Claim 20 wherein said insulated gate means (238) comprises tungsten disilicide.

Claim 26

The invention according to Claim 17 wherein said notches (118, 120, 122) are anisotropically etched and oxidized.

Claim 27

The invention according to Claim 16 wherein: said main electrodes (150 and 152) are connectable to an AC load line (160, 162); said gate electrode means (132) is connectable to gate potential source means (166); such that said gate electrode means (166) is positive with respect to one of said main electrodes (150) during the first half cycle of said AC line, and is positive with respect to the other of said main electrodes (152) during the second half cycle of said AC line; such that during the first half cycle of said AC line, current flows from said other main electrode (152) through the other source region (142), through said other channel region (146), through said substrate drift region (148) around the bottom of said notch (118), through said one channel region (144), through said one source region (140) to said one main electrode (150); and such that during the second half cycle of said AC line, current flows from said one main electrode (150) through said source region (140), through said one channel region (144), through said substrate- drift region (148) around the bottom of said notch (118), through said other channel region (146), through said other source region (142) to said other main electrode (152).

Claim 28

The invention according to Claim 25 wherein said FET (102) has an OFF state in the absence of said given gate potential, with the junction (158) between said substrate drift region (148) and said one channel region (144) blocking current flow toward said one main electrode (150), and with the junction (154) between said substrate drift region (148) and said other channel region (146) blocking current flow toward said other main electrode (152).

Claim 29

The invention according to Claim 26 wherein said gate electrode means (132) is referencable in said OFF state to one of said main electrodes (150), and wherein said notch (118) increases the length of said substrate drift region current path to thus provide higher voltage blocking capability in said OFF state, without increasing the lateral dimension along said top major surface (106).

Claim 30

The invention according to Claim 27 wherein: during said first half cycle of said AC line, current flows from said other main electrode (152) momentarily across a forward biased junction (154) therebelow between said first top layer (110) and said substrate drift region (148), and then flows through said one channel region (144) to said one source region (140) and said one main electrode -(150, the falling potential in said substrate (104) across said forward biased junction (154) relative to said gate electrode means (132) causing said gate electrode means (132) to attract given polarity carriers to said other channel region (146) to invert the latter to said one conductivity type, such that the main current path during said first half cycle is from said other main electrode (152) through said other source region (142), through said other channel region (146), through said substrate drift region (148) around the bottom of said notch (118), through said one channel region (144), through said one source region (140) to said one main electrode (150); and such that during the second half cycle of said AC line, current flows from said one main electrode (150) momentarily across a forward biased junction (158) therebelow between said first top layer (110) and said substrate drift region (148) and then flows through said other channel region (146) to said other source region (142) and said other main electrode (152), the falling potential in said substrate (104) across said last mentioned forward biased junction (158) relative to said gate electrode means (132) causing said gate electrode means (132) to attract given polarity carriers to said one channel region (144) to invert the latter to said one conductivity type, such that the main current path during said second half cycle is from said one main electrode (150) through said one source region (140), through said one channel region (144), through said substrate drift region (148) around the bottom of said notch (118), through said other channel region (146), through said other source region (142) to said other main electrode (152).

Claim 31

A lateral power FET (102) comprising: a substrate (104) of semiconductor material including a lateral n epitaxial layer (104); a p type layer (110) on said lateral n epitaxial layer (104); an n type region (112) embedded in said p type layer (110); a notch (118) extending downwardly through said n type region (112), through said p type layer (110), and into said n epitaxial layer (104); insulated gate means (132) disposed in said notch (118) including portions in close proximity to and insulated from the generally vertical regions (144 and 146) in said p type layer (110) on opposite sides of said notch (118), and adapted for application of electrical gate potential for producing controllable electric fields in said last mentioned vertical regions (144 and 146); a pair of main electrodes (150 and 152) each conductively communicating with a respective one of said embedded n type regions (140 and 142) on opposite sides of said notch (118) for serving as an electron current source when a negative voltage is applied to one of said main electrodes relative to the voltage on the other of said main electrodes, and serving as an anode when a positive voltage is applied to said one main electrode relative to the voltage on said other main electrode; whereby upon application of voltage of either polarity to said main electrodes (150 and 152), current flow in either direction between said embedded n type regions (140 and 142) on opposite. sides of said notch (118) is controllable by controlling said potential on said gate means (132).

Claim 32

A lateral power FET (102) comprising: a substrate (104) of semiconductor material including a lateral n epitaxial layer (104); a p type layer (110) on said lateral n epitaxial layer (104); an n type region (112) embedded in said p type layer (110); a notch (118) extending downwardly through said n type region (112), through said p type layer (110), and into said n epitaxial layer (104); insulated gate means (132) disposed in said notch (118) including portions in close proximity to and insulated from the generally vertical regions (144 and 146) in said p type layer (110) on opposite sides of said notch (118), and adapted for application of electrical gate potential for producing controllable electric fields in said last mentioned vertical regions (144 and 146); a pair of main electrodes (150 and 152) each conductively communicating with a respective one of said embedded n type regions (140 and 142) on opposite sides of said notch (118) for serving as an electron current source when a negative voltage is applied to one of said main electrodes relative to the voltage on the other of said main electrodes, and serving as an anode when a positive voltage is applied to said one main electrode relative to the voltage on said other main electrode; whereby upon application of voltage of either polarity to said main electrodes (150 and 152), current flow in either direction between said embedded n type regions (140 and 142) on opposite. sides of said notch (118) is controllable by controlling said potential on said gate means (132).

Claim 33

The invention according to Claim 29 wherein the conductive current path through said substrate (104) extends generally vertically along opposite sides of said notch (118) and around the bottom thereof so as to increase the drift region path length through said n epitaxial layer (104) of said FET (102) without increasing the lateral dimension, whereby to afford higher voltage blocking capability in a smaller lateral area.

Claim 34

The invention according to Claim 30 wherein said notch (268, Figure 21) extends downwardly into said n epitaxial layer (202) a substantial distance below said gate means (238) to substantially diminish attraction of holes by said gate means (238) from said n epitaxial layer (202) toward the edges of said notch (268), to prevent unwanted inducement of conductive p channels between said p layers (204 and 280) on opposite sides of said notch (268) in an OFF state of said FET, to afford increased OFF state voltage blocking capability.

Claim 35

The invention according to Claim 31 wherein said notch (268) extends downwardly into said n epitaxial layer (202) to a depth substantially below said p type layers (204 and 280) on opposite sides of said notch (268), and said gate means (238) extends downwardly into said notch (268) to about the depth of the junctions (260 and 264) between said p layers (204 and 280) and said epitaxial layer (202).

Claim 36

The invention according to Claim 32 wherein the portion (228) of said notch (268) below said gate means (238) comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

Claim 37

A bidirectional lateral FET (102) on a semiconductor body (104), comprising: a first source region (140); a common drain region (148) ; a first channel region (144) extending generally vertically between said first source region (140) and said common drain region (148); a second source region (142); a second channel region (146) extending generally vertically between said second source region (142) and said common drain region (148); said first channel region (144) and said common drain region (148) being contiguous to define a junction (158) therebetween. said second channel region (146) and said common drain region (148) being contiguous to define a junction (154) therebetween. a notch (118) extending between and separating said first and second channel regions (144 and 146) and said first and second mentioned junctions (158) and 154), and extending into said drain region (148) to direct the drift region path therearound between said channel regions (144 and 146); insulated gate electrode means (132) in said notch (118) and including at least portions proximate and insulated from said first and second channel regions (144 and 146) for controllably inducing electric fields in said channel regions (144 and 146); whereby when a voltage is applied to said first source region (140) which is negative with respect to said second source region (142), electron flow from said first source region (140) to said second source region (142) is controllable by controlling a voltage applied to said gate electrode means (132), and when a voltage is applied to said second source region (142) which is negative with respect to said first source region (140), electron flow from said second source region (142) to said first source region (140) is controllable by controlling a voltage applied to said gate electrode means (132); said FET (102) having an OFF state in the absence of said voltage on said gate electrode means (132), said notch (118) providing an increased drift region path to increase the voltage blocking capability of said FET (102) in said OFF state.

Claim 38

A bidirectional lateral FET (102) on a semiconductor body (104), comprising: a first source region (140); a common drain region (148) ; a first channel region (144) extending generally vertically between said first source region (140) and said common drain region (148); a second source region (142); a second channel region (146) extending generally vertically between said second source region (142) and said common drain region (148); said first channel region (144) and said common drain region (148) being contiguous to define a junction (158) therebetween. said second channel region (146) and said common drain region (148) being contiguous to define a junction (154) therebetween. a notch (118) extending between and separating said first and second channel regions (144 and 146) and said first and second mentioned junctions (158) and 154), and extending into said drain region (148) to direct the drift region path therearound between said channel regions (144 and 146); insulated gate electrode means (132) in said notch (118) and including at least portions proximate and insulated from said first and second channel regions (144 and 146) for controllably inducing electric fields in said channel regions (144 and 146); whereby when a voltage is applied to said first source region (140) which is negative with respect to said second source region (142), electron flow from said first source region (140) to said second source region (142) is controllable by controlling a voltage applied to said gate electrode means (132), and when a voltage is applied to said second source region (142) which is negative with respect to said first source region (140), electron flow from said second source region (142) to said first source region (140) is controllable by controlling a voltage applied to said gate electrode means (132); said FET (102) having an OFF state in the absence of said voltage on said gate electrode means (132), said notch (118) providing an increased drift region path to increase the voltage blocking capability of said FET (102) in said OFF state.

Claim 39

The invention according to Claim 34 wherein the electron flow path in one direction is from first source region (140) downwardly through said first channel region (144) along one side of said notch (118), then downwardly into said drain region (148) along said one side of said notch (118), then around the bottom of said notch (118), then upwardly through said drain region (148) along the other side of said notch (118) then upwardly through said second channel region (146) along said other side of said notch (118) to said second source region (142), and the electron flow in the reverse direction follows the same path.

Claim 40

The invention according to Claim 35 wherein said first and second source regions (140 and 142) are laterally spaced along a top major surface (106) of said semiconductor body (104) by said notch (118) therebetween, and said first and second channel regions (144 and 146) are laterally spaced by said notch (118) therebetween.

Claim 41

The invention according to Claim 36 wherein said notch (268, Figure 21) extends downwardly into said drift region (258) of said common drain region a substantial distance below said gate electrode means (238) to substantially diminish attraction of carriers by said gate electrode means (238) from said drift region (258) toward the edges of said notch (268), to prevent unwanted inducement of conduction channels in said OFF state, to afford increased OFF state voltage blocking capability of said FET.

Claim 42

The invention according to Claim 37 wherein said notch (268) extends downwardly into said drift region (258) to a depth substantially below said channel regions (254 and 262), and said gate electrode means (238) extends downwardly to about the depth of the junctions (260 and 264) between said channel regions (254 and 262) and said drift region (258).

Claim 43

The invention according to Claim 38 wherein the portion (228) of said notch (268) below said gate electrode means (238) comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

Claim 44

Bidirectional laterally integrated power switching plural FET structure (102) comprising: a semiconductor body (104) having a top major surface (106) and including a lateral substrate layer (104) of one conductivity type at a predetermined depth below said top major surface (106); a top layer (110) of opposite conductivity type on said substrate layer (104); a plurality of top regions (112, 114, 116) of said one conductivity type formed in said top layer (110) and laterally spaced along said top major surface (106); a plurality of notches (118, 120, 122), each extending downwardly from said top major (106) surface through a respective one of said top regions (112, 114, 116) and through said top layer (110) into said substrate layer (104), each notch (such as 118) separating its repsective said top region (112) into right and left source regions (140 and 142) laterally spaced along said top major surface (106) by said notch (118) therebetween, each notch (such as 118) also separating the portion of said top layer (110) below its respective said top region (112) into right and left channel regions (144 and 146) below said right and left source regions (140 and 142) and likewise laterally spaced by the respective said notch (118) extending therebetween, each notch (such as 118) further providing a drift region (148) path through said substrate layer (104), which path (148) extends generally vertically along the sides of said notch (118) and around the bottom thereof to provide substantially increased drift region path length without increased lateral dimension; a plurality of first main electrodes (150, 151) connected respectively to said left source regions; a plurality of second main electrodes (152, 153) connected respectively to said right source regions; insulated gate electrode means (132, 134, 136) in said notches (118, 120, 122) including portions proximate said right and left channel regions for attracting given polarity carriers to invert said channel regions to said one conductivity type in response to given gate potential, such that current may flow in either direction between said first main electrodes (150, 151) and said second main electrodes (152, 153), the conductive current path for each FET being from said left source region downwardly through a generally vertical left said channel region along the left side of said notch, then further downwardly into said drift region along said left side of said notch, then around the bottom of said notch in said drift region in said substrate layer, then upwardly along the right side of said notch and said drift region, then upwardly along a generally vertical said right channel region to said right source region, with the same path conducting current in the reverse direction from said right source region to said left source region for each said FET.

Claim 45

Bidirectional laterally integrated power switching plural FET structure (102) comprising: a semiconductor body (104) having a top major surface (106) and including a lateral substrate layer (104) of one conductivity type at a predetermined depth below said top major surface (106); a top layer (110) of opposite conductivity type on said substrate layer (104); a plurality of top regions (112, 114, 116) of said one conductivity type formed in said top layer (110) and laterally spaced along said top major surface (106); a plurality of notches (118, 120, 122), each extending downwardly from said top major (106) surface through a respective one of said top regions (112, 114, 116) and through said top layer (110) into said substrate layer (104), each notch (such as 118) separating its repsective said top region (112) into right and left source regions (140 and 142) laterally spaced along said top major surface (106) by said notch (118) therebetween, each notch (such as 118) also separating the portion of said top layer (110) below its respective said top region (112) into right and left channel regions (144 and 146) below said right and left source regions (140 and 142) and likewise laterally spaced by the respective said notch (118) extending therebetween, each notch (such as 118) further providing a drift region (148) path through said substrate layer (104), which path (148) extends generally vertically along the sides of said notch (118) and around the bottom thereof to provide substantially increased drift region path length without increased lateral dimension; a plurality of first main electrodes (150, 151) connected respectively to said left source regions; a plurality of second main electrodes (152, 153) connected respectively to said right source regions; insulated gate electrode means (132, 134, 136) in said notches (118, 120, 122) including portions proximate said right and left channel regions for attracting given polarity carriers to invert said channel regions to said one conductivity type in response to given gate potential, such that current may flow in either direction between said first main electrodes (150, 151) and said second main electrodes (152, 153), the conductive current path for each FET being from said left source region downwardly through a generally vertical left said channel region along the left side of said notch, then further downwardly into said drift region along said left side of said notch, then around the bottom of said notch in said drift region in said substrate layer, then upwardly along the right side of said notch and said drift region, then upwardly along a generally vertical said right channel region to said right source region, with the same path conducting current in the reverse direction from said right source region to said left source region for each said FET.

Claim 46

The invention according to Claim 40 wherein said notch (268, Figure 21) extends downwardly into said drift region (258) to a depth substantially below said channel regions (254 and 262), and said gate electrode means (238) extends downwardly to about the depth of the junctions (260 and 264) between said channel regions (254 and 262) and said drift region (258), the portion (228) of said notch (268) below said gate electrode means (238) comprising anodized single crystalline porous silicon oxidized to a substantially insulative condition to substantially diminish attraction of carriers by said gate electrode means (238) from said drift region (258) toward the edges of said notch (268), to prevent unwanted inducement of conduction channels in an OFF state of said FET to increase OFF state voltage blocking capability.

Claim 47

The invention according to Claim 41 wherein the drift region current path between said first and second main electrodes extends from the respective said source regions downwardly through the respective said channel regions and downwardly and around the bottom of the respective said notches so as to increase the drift region current path length and afford higher OFF state voltage blocking capability, without increasing the lateral dimension along said top major surface, whereby to afford high density, high voltage bidirectional FET structure.