Multiple access system and method

Claim 2

Method for packet communication in a multiple access system having a communication medium shared by a plurality of users through a plurality of channels in which the probability P, j of packet transmission on the i-th channel for the j-th user is controlled so that the transmission mode varies between a non-deterministic mode incurring packet collision and a deterministic mode free of packet collisions, characterized in that each probability value P ij is permanently updated in such a manner that P ij is increased, if no collision occurs in the i-th channel or if the channel is detected to be idle and is decreased otherwise.

Claim 3

A multiple access system for performing packet communication involving sharing of a single communication medium by a plurality of users through a plurality of channels such that each user monitors a state of each channel and probability of packet transmission is controlled in accordance with a monitored result, comprising: - an interface section (52) for linking data together as a packet; - modem section (54) for modulating/demodulating a packet; - an RF section (55) for converting an IF signal to a high frequency transmission signal and vice versa, characterized in that said modem section includes - a carrier detector (69) for detecting whether or not the channel is being used and for generating one of empty and busy signals; -further characterized by a network control section (53) for performing access control, said network control section (53) including - collision detector (701) for detecting a transmitting packet and a delayed receiving packet so as to detect a collision of the transmitting packet with another transmitting packet, said collision detector (701) generating a success signal when the transmitting packet and the delayed receiving packet coincide with each other and a collision signal when the transmitting packet and the delayed received packet do not coincide, - a retransmitter (702) for retransmitting a packet identical with the transmitting packet when the transmitting packet collides with said delayed receiving packet, and - a control circuit (79) for receiving a slot sync pulse, one of the busy and empty signals, one of the success and collision signals, and a packet arrival pulse, and for generating a control signal to control packet transmission; -the control circuit (79) comprises: ―a memory (82) for storing parameter data the number of which corresponds to the number of the channels; - a counter (709) for counting the slot sync pulse in units of one frame, and subtracting the number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data; - a selector (800) for receiving the subtracted data and the count data and for reading out of the memory

Claim 4

A multiple access system for performing packet communication involving sharing of a single communication medium by a plurality of users through a plurality of channels such that each user monitors a state of each channel and probability of packet transmission is controlled in accordance with a monitored result, comprising: - an interface section (52) for linking data together as a packet; - modem section (54) for modulating/demodulating a packet; - an RF section (55) for converting an IF signal to a high frequency transmission signal and vice versa, characterized in that said modem section includes - a carrier detector (69) for detecting whether or not the channel is being used and for generating one of empty and busy signals; -further characterized by a network control section (53) for performing access control, said network control section (53) including - collision detector (701) for detecting a transmitting packet and a delayed receiving packet so as to detect a collision of the transmitting packet with another transmitting packet, said collision detector (701) generating a success signal when the transmitting packet and the delayed receiving packet coincide with each other and a collision signal when the transmitting packet and the delayed received packet do not coincide, - a retransmitter (702) for retransmitting a packet identical with the transmitting packet when the transmitting packet collides with said delayed receiving packet, and - a control circuit (79) for receiving a slot sync pulse, one of the busy and empty signals, one of the success and collision signals, and a packet arrival pulse, and for generating a control signal to control packet transmission; -the control circuit (79) comprises: ―a memory (82) for storing parameter data the number of which corresponds to the number of the channels; - a counter (709) for counting the slot sync pulse in units of one frame, and subtracting the number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data; - a selector (800) for receiving the subtracted data and the count data and for reading out of the memory

Claim 5

(82) parameter data corresponding to the subtracted data and the count data; - an arithmetic operation unit (81) for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said memory (82); and - a pattern generator (83) for receiving the parameter data corresponding to the counter data and generating the control signal using as a probability the updated parameter data from said selector (800), thereby opening a gate circuit (78) in accordance with the probability.

Claim 6

(82) parameter data corresponding to the subtracted data and the count data; - an arithmetic operation unit (81) for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said memory (82); and - a pattern generator (83) for receiving the parameter data corresponding to the counter data and generating the control signal using as a probability the updated parameter data from said selector (800), thereby opening a gate circuit (78) in accordance with the probability.

Claim 7

A system according to claim 2, wherein said modem section (54) further includes: - a modulator (67) for modulating the packet; ―a demodulator (68) for demodulating a modulated packet to generate a demodulated signal; and ―a slot sync signal detector (600) for receiving the demodulated signal to extract the slot sync signal constantly propagated along the channel and for generating and supplying the slot sync signal to said network control section (53).

Claim 8

A system according to claim 2, wherein said network control section (53) further includes: - a buffer (77) for supplying the packet arrival pulse to said control circuit (79) every time said buffer (77) receives the packet; - a gate circuit (78) which is turned on in response to the control signal supplied from said control circuit

Claim 9

(79) thereto so as to pass the packet therethrough; - a delay circuit (700) for delaying the packet from said gate circuit (78) and for supplying a delayed packet to said retransmitter (702) and said collision detector; and - an address filter (703) for receiving only the packet destined therefor and supplying the packet to said interface section (52).

Claim 10

(79) thereto so as to pass the packet therethrough; - a delay circuit (700) for delaying the packet from said gate circuit (78) and for supplying a delayed packet to said retransmitter (702) and said collision detector; and - an address filter (703) for receiving only the packet destined therefor and supplying the packet to said interface section (52).

Claim 11

A system according to claim 2, wherein said control circuit comprises: - a second memory (1003) for storing single parameter data for controlling a sequence .flow; ―a second selector (1002) for reading out the single parameter data from said second memory (1003); - a second arithmetic operation unit (1004) for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory; - a multiplier (1001) for multiplying the updated subtracted parameter data from said selector (800) by the updated single parameter data from said second selector (1002); and that the - pattern generator (83) receives multiplied parameter data from said multiplier and generating the control signal using as a probability the multiplied parameter data from said multiplier (1001), thereby opening said gate (78) circuit in accordance with the probability.

Claim 12

A system according to claim 2, wherein said arithmetic operation (81) unit comprises: - a function generator (89) for generating a function value 6, δ=1 under a first condition that one of the empty and success signals is detected; δ=-l under a second condition excluding the first condition, and - first arithmetic logic circuit (90) for receiving the function value δ so as to perform an operation P l ←P l +aδ where 1=1 ... L, L being the number of channels, 0≤P l ≤1, and a is a small positive number.

Claim 13

A system according to claim 6 further comprising: - second arithmetic operation circuit (93) for performing an operation λ←λ-β(ΣP l -1) where λ is a Lagrangean constant, 0≤λ, and β is a small positive number; and - third arithmetic operation circuit (91) for computing the Lagrangean constant λ in accordance with λ←min (λ, λ 0 ) for λ 0 ≤1, - whereby said first arithmetic operation circuit (90) is caused to perform an operation P l ←P l ,+a(δ+λ).

Claim 14

A system according to claim 7 further comprising an averaging circuit (92) for producing â L where a is an average of arrival frequency, whereby said second arithmetic operation circuit (93) performs an operation λ←λ-β(ΣP l ,-âL).

Claim 15

A system according to claim 2, wherein said network control section (33) further includes: ―a channel collision detector (1020) for detecting errors of all the received packets, said control circuit (1021) receiving a collision signal from said channel collision detector (1021).

Claim 16

A system according to claim 9, wherein said network control section further includes: ―a buffer (77) for supplying the packet arrival pulse to said control circuit (1021) every time said buffer receives the packet; - a gate circuit (78) which is turned on in response to the control signal supplied from said control circuit (1021) so as to pass the packet therethrough; - a delay circuit (700) for delaying the packet from said gate circuit (78) and for supplying a delayed packet to said retransmitter (702) and said collision detector (701) and - an address filter (703) for receiving only the packet destined thereto and supplying the packet to said interface section (52).

Claim 17

A system according to claim 9, wherein said control circuit comprises: - a first memory (82) for storing parameter data the number of which corresponds to the number of the channels; -a second memory (1003) for storing single parameter data for controlling a sequence flow; - counter (709) for counting the slot sync pulse in units of one frame, subtracting a number of slots corresponding to a transmission delay time from count data thereof so as to obtain subtracted data; - a first selector (800) for receiving the subtracted data and the count data and reading out parameter data corresponding to the subtracted data and the count data; - a first arithmetic operation unit (1000) for receiving the parameter data corresponding to the subtracted data, updating the parameter data, and supplying updated parameter data to said first memory (82); - a second selector (1002) for reading out the single parameter data from said second memory (1003); - a second arithmetic operation unit (1004) for receiving and updating the single parameter data, thereby restoring updated single parameter data in said second memory (1003); - a multiplier (1001) for multiplying the updated subtracted parameter data from said first selector (800) by the updated single parameter data from said second selector (1002) and - a pattern generator (83) for receiving multiplied parameter data from said multiplier (1001) and generating the control signal using as a probability the multiplied parameter data from said multiplier (1001), thereby opening said gate circuit (78) in accordance with the probability.

Claim 18

A system according to claim 5 or 11, wherein said second arithmetic operation circuit (1004) comprises: - a function generator (1007) for generating a function value ξ where ξ=-1 under a first condition that the collision signal is detected and ξ=ξ 0 >0 under a second condition excluding the first condition; and - an arithmetic logic circuit (1008) for receiving and updating the function value ξ in accordance with the updated single parameter data so as to perform an operation P←P+rξ, where P is the single parameter data 0≤P≤1, is the function value and r is a small positive number.