EP0096885A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Synchronizing circuit for detecting and interpolating sync signals contained in digital signal
Assignee: Toshiba Corp
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Filing: 1983-06-14
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Granted: —
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Expires: 2003-06-14
Abstract
Abstract A synchronous circuit comprises a sync signal detecting circuit (3) connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect the sync signal in each frame, and a sync protecting circuit (5, 6, 8) for producing a sync control signal synchronized with the detection of the sync signal and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter (7) for counting the number of frames in which the sync signals are not detected. A circuit (10, 11, 12, 13) is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit in a case where noise is output from the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter (7).
Inventors
- 👤 Jun Inagawa
- 👤 Masahide Nagumo
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 02:04
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/10527; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
591 words
A synchronizing circuit comprising: frame sync signal detecting circuit means (3) connected to receive a digital input signal having a plurality of frames each consisting of N bits and a frame sync signal for producing a sync detect output signal synchronized with the frame sync signal; first counting means (5) connected to receive clock signals and the sync detect output signal of said frame sync signal detecting circuit means (3) for producing a first output signal or second output signal respectively synchronized with or not synchronized with the sync detect output signal each time N clock signals are counted, the first output signal being produced when said frame sync signal detecting circuit means (3) detects the frame sync signal and the second output signal being produced when said frame sync signal detecting circuit means (3) fails to detect the frame sync signal, said first counting means (5) being so arranged to be cleared by the sync detect output signal of said frame sync signal detecting circuit means (3); first window generating means (6) responsive to each of said first and second output signals of said first counting means (5) for generating a window output signal; second counting means (7) connected to receive the window output signal of said first window generating means (6) and sync detect output signal of said sync signal detecting circuit means (3) for producing an output signal which has its output state changed from a first state to a second state when said second counting means counts a given number of the window output signals of said first window generating means (6) during said sync signal detecting circuit means (3) failing to detect the frame sync signals, said second counting means (7) being cleared by the sync detect output signal of said frame sync signal detecting circuit means (3) to the first output state when said first counting means (5) is synchronized with said frame sync signal detecting circuit means (3); a first gate circuit (4) connected between said sync signal detecting circuit means (3) and said first and second counting means (5, 7) for, when enabled, applying the output signal of said sync signal detecting circuit means to said first and second counting means; a second gate circuit (10) connected to receive the output signal of said sync signal detecting circuit means, said second gate circuit being enabled by the output signal of said second counting means (7) when the output signal of said second counting means is in said second state; third counting means (11) for counting the clock pulses to produce an output signal each time said third counting means counts N clock pulses, said third counting means being cleared by the output signal of said sync signal detecting circuit means passing through said first or second gate circuit (4, 10); a second window generating means (12) responsive to the output signal of said'third counting means (11) for producing a window output signal; and means (8) responsive to said second counting means for selectively coupling one of the output signals of said first and second window generating means to said first gate circuit to enable said first gate circuit, such that the window output signal of said first window generating means is applied to said first gate circuit when the output signal of said second counting means is in said first state and the window output signal of said second window generating means is applied to said first gate circuit when the output signal of said second counting means is in said second state.
Claim 2
Dependent Claim
591 words
A synchronizing circuit comprising: frame sync signal detecting circuit means (3) connected to receive a digital input signal having a plurality of frames each consisting of N bits and a frame sync signal for producing a sync detect output signal synchronized with the frame sync signal; first counting means (5) connected to receive clock signals and the sync detect output signal of said frame sync signal detecting circuit means (3) for producing a first output signal or second output signal respectively synchronized with or not synchronized with the sync detect output signal each time N clock signals are counted, the first output signal being produced when said frame sync signal detecting circuit means (3) detects the frame sync signal and the second output signal being produced when said frame sync signal detecting circuit means (3) fails to detect the frame sync signal, said first counting means (5) being so arranged to be cleared by the sync detect output signal of said frame sync signal detecting circuit means (3); first window generating means (6) responsive to each of said first and second output signals of said first counting means (5) for generating a window output signal; second counting means (7) connected to receive the window output signal of said first window generating means (6) and sync detect output signal of said sync signal detecting circuit means (3) for producing an output signal which has its output state changed from a first state to a second state when said second counting means counts a given number of the window output signals of said first window generating means (6) during said sync signal detecting circuit means (3) failing to detect the frame sync signals, said second counting means (7) being cleared by the sync detect output signal of said frame sync signal detecting circuit means (3) to the first output state when said first counting means (5) is synchronized with said frame sync signal detecting circuit means (3); a first gate circuit (4) connected between said sync signal detecting circuit means (3) and said first and second counting means (5, 7) for, when enabled, applying the output signal of said sync signal detecting circuit means to said first and second counting means; a second gate circuit (10) connected to receive the output signal of said sync signal detecting circuit means, said second gate circuit being enabled by the output signal of said second counting means (7) when the output signal of said second counting means is in said second state; third counting means (11) for counting the clock pulses to produce an output signal each time said third counting means counts N clock pulses, said third counting means being cleared by the output signal of said sync signal detecting circuit means passing through said first or second gate circuit (4, 10); a second window generating means (12) responsive to the output signal of said'third counting means (11) for producing a window output signal; and means (8) responsive to said second counting means for selectively coupling one of the output signals of said first and second window generating means to said first gate circuit to enable said first gate circuit, such that the window output signal of said first window generating means is applied to said first gate circuit when the output signal of said second counting means is in said first state and the window output signal of said second window generating means is applied to said first gate circuit when the output signal of said second counting means is in said second state.
Claim 3
Dependent Claim
498 words
A synchronizing circuit comprising: frame sync signal detecting circuit means (3) connected to receive a digital input signal having a plurality of frames each consisting of N bits and a frame sync signal for producing a sync detect output signal synchronized with the frame sync signal; first counting means (5) connected to receive clock signals and the sync detect output signal of said frame sync signal detecting circuit means (3) for producing a first output signal or second output signal respectively synchronized with or not synchronized with the sync detect output signal each time N clock signals are counted, the first output signal being produced when said frame sync signal detecting circuit means (3) detects the frame sync signal and the second output signal being produced when said frame sync signal detecting circuit means (3) fails to detect the frame sync signal, said first counting means (5) being so arranged to be cleared by the sync detect output signal of said frame sync signal detecting circuit means (3); window generating means (6) responsive to each of said first and second output signals of said first counting means for producing a window output signal; second counting means (7) connected to receive the window output signal of said window generating means (6) and the output signal of said sync signal detecting circuit means (3) for producing an output signal which has its output state changed from a first statetra second state when said second counting means counts a given number of the window output signals of said window generating means (6) during said sync signal detecting circuit means (3) failing to detect the frame sync signals, said second counting means (7) being cleared by the sync detect output signal of said frame sync signal detecting circuit means (3) to the first output state when said first counting means (5) is synchronized with said frame sync signal detecting circuit means (3); a first gate circuit (4) connected between said sync signal detecting circuit means (3) and said first counting means (5) for, when enabled, applying the output signal of said sync signal detecting circuit means to said first counting means; a second gate circuit (10) connected between said sync signal detecting circuit means (3) and said second counting means (7), said second gate circuit being enabled by the window output signal of said window generating means to apply the output signal of said sync signal detecting circuit means to said second counting means; and means (8) responsive to said second counting means (7) to apply the window output signal of said window generating means (6) to said first gate circuit (4) when the output signal of said second counting means is in said first state so that said first gate circuit is enabled each time the window output signal is produced, and to enable said first gate circuit (4) until said second counting means (7) is cleared when the output signal of said second counting means is in said second state.
Claim 4
Dependent Claim
498 words
A synchronizing circuit comprising: frame sync signal detecting circuit means (3) connected to receive a digital input signal having a plurality of frames each consisting of N bits and a frame sync signal for producing a sync detect output signal synchronized with the frame sync signal; first counting means (5) connected to receive clock signals and the sync detect output signal of said frame sync signal detecting circuit means (3) for producing a first output signal or second output signal respectively synchronized with or not synchronized with the sync detect output signal each time N clock signals are counted, the first output signal being produced when said frame sync signal detecting circuit means (3) detects the frame sync signal and the second output signal being produced when said frame sync signal detecting circuit means (3) fails to detect the frame sync signal, said first counting means (5) being so arranged to be cleared by the sync detect output signal of said frame sync signal detecting circuit means (3); window generating means (6) responsive to each of said first and second output signals of said first counting means for producing a window output signal; second counting means (7) connected to receive the window output signal of said window generating means (6) and the output signal of said sync signal detecting circuit means (3) for producing an output signal which has its output state changed from a first statetra second state when said second counting means counts a given number of the window output signals of said window generating means (6) during said sync signal detecting circuit means (3) failing to detect the frame sync signals, said second counting means (7) being cleared by the sync detect output signal of said frame sync signal detecting circuit means (3) to the first output state when said first counting means (5) is synchronized with said frame sync signal detecting circuit means (3); a first gate circuit (4) connected between said sync signal detecting circuit means (3) and said first counting means (5) for, when enabled, applying the output signal of said sync signal detecting circuit means to said first counting means; a second gate circuit (10) connected between said sync signal detecting circuit means (3) and said second counting means (7), said second gate circuit being enabled by the window output signal of said window generating means to apply the output signal of said sync signal detecting circuit means to said second counting means; and means (8) responsive to said second counting means (7) to apply the window output signal of said window generating means (6) to said first gate circuit (4) when the output signal of said second counting means is in said first state so that said first gate circuit is enabled each time the window output signal is produced, and to enable said first gate circuit (4) until said second counting means (7) is cleared when the output signal of said second counting means is in said second state.
References Cited (Backward Citations)
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