Patent US3456142A successfully refreshed from Google Patents.
EP0096779A2
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Multi-bit error scattering arrangement to provide fault tolerant semiconductor memory
Assignee: International Business Machines Corp
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Filing: 1983-05-27
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Granted: —
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Expires: 2003-05-27
Abstract
Abstract A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n x m) of separate memory chips (71) arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n' (16) word m (72) bit position buffer during a memory read operation. Steering logic (35) responsive to control signals (R5-R8) is disposed between the memory and the buffer which permits the n (32) chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column (20) may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location. An additional control signal (R2) may be used to control an address permutation logic (40) for helping to achieve the same purpose.
Inventors
- 👤 George L. Bond
- 👤 Frank P. Cartman
- 👤 Philip M. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 11:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
235 words
A very large memory system comprising in combination: a large plurality of individual memory chips (11), said chips being arranged in a matrix (10) of n rows and m columns (12-15), each said chip having k x L individually addressable bit positions some of which are defective; k x L x n memory addresses, each of which accesses a data word of m bit positions; a buffer (20-23) for storing n' words each comprising m bit positions; and data bus means for connecting the write input and the read output of each said chip in each said column of said memory matrix to one of the n' buffer storage positions associated with each one of said memory columns; characterized by: means (35, 36, 40) for changing the connective relationship of said n' buffer storage positions associated with each bit position of said buffer relative to the position of said n chips in the corresponding memory matrix column in response to control signals (R5-R8, R2) developed from an error map of said memory, said control signals causing said relationship of said chips to said n' buffer positions in at least one of the columns of the matrix which has one defective bit position aligned with a defective bit position in another column, to be altered so that said one defective bit position is thereafter associated with a memory address containing no such other defective bit position.
Claim 2
Dependent Claim
235 words
A very large memory system comprising in combination: a large plurality of individual memory chips (11), said chips being arranged in a matrix (10) of n rows and m columns (12-15), each said chip having k x L individually addressable bit positions some of which are defective; k x L x n memory addresses, each of which accesses a data word of m bit positions; a buffer (20-23) for storing n' words each comprising m bit positions; and data bus means for connecting the write input and the read output of each said chip in each said column of said memory matrix to one of the n' buffer storage positions associated with each one of said memory columns; characterized by: means (35, 36, 40) for changing the connective relationship of said n' buffer storage positions associated with each bit position of said buffer relative to the position of said n chips in the corresponding memory matrix column in response to control signals (R5-R8, R2) developed from an error map of said memory, said control signals causing said relationship of said chips to said n' buffer positions in at least one of the columns of the matrix which has one defective bit position aligned with a defective bit position in another column, to be altered so that said one defective bit position is thereafter associated with a memory address containing no such other defective bit position.
Claim 3
Independent Claim
60 words
The system recited in claim I in which said means for changing said connective relationship includes a data steering logic (35) connecting each of said n chips with a selected one of said n' buffer positions determined by said control signals (R5-R8), and a fault alignment exclusion register (36) connected to supply said control signals to said data steering logic.
Claim 4
Independent Claim
13 words
The system recited in claim I or 2 in which n' equals n.
Claim 5
Independent Claim
81 words
The system recited in claim or 2 in which n' is an integral submultiple of n, and said means for changing said connective relationship includes address permutation logic (40) connected to each chip in said array to permit a first group of n' chips to be actively associated in a data transfer relatiopship with said buffer in place of a second group of n' chips whereby one chip containing a defect is swapped for an associated chip containing no such defect.
Claim 6
Dependent Claim
246 words
In a memory system comprising a relatively large number of individual memory chips, each of which has a relatively large number of individually addressable bit storage positions some of which are defective and in which said chips are arranged in a matrix of n rows and m columns to provide a plurality of word storage locations, each of which comprises m bit positions and some of which include at least two aligned defective bit positions, and further provided with an error correcting system for correcting a single-bit error in any bit position of a word read from memory and detecting errors in more than one position that are uncorrectable, an improved method of selectively repositioning each said defective bit position within its respective column to prevent more than one of said defective bit positions from being aligned at any one address of said memory, said method being characterized by: transferring a plurality of words from a plurality of known memory addresses in parallel to a plurality of word buffers, each said address being associated with a different row of chips in said memory; and selectively changing the normal relationship between each chip in a selected column of said memory and corresponding bit storage positions of said word buffers to cause one chip having an identified defective storage location which might cause an uncorrectable error for a data word stored at that address, to be replaced by another chip which is defect free at that storage position.
Claim 7
Dependent Claim
246 words
In a memory system comprising a relatively large number of individual memory chips, each of which has a relatively large number of individually addressable bit storage positions some of which are defective and in which said chips are arranged in a matrix of n rows and m columns to provide a plurality of word storage locations, each of which comprises m bit positions and some of which include at least two aligned defective bit positions, and further provided with an error correcting system for correcting a single-bit error in any bit position of a word read from memory and detecting errors in more than one position that are uncorrectable, an improved method of selectively repositioning each said defective bit position within its respective column to prevent more than one of said defective bit positions from being aligned at any one address of said memory, said method being characterized by: transferring a plurality of words from a plurality of known memory addresses in parallel to a plurality of word buffers, each said address being associated with a different row of chips in said memory; and selectively changing the normal relationship between each chip in a selected column of said memory and corresponding bit storage positions of said word buffers to cause one chip having an identified defective storage location which might cause an uncorrectable error for a data word stored at that address, to be replaced by another chip which is defect free at that storage position.
Claim 8
Dependent Claim
67 words
The method recited in claim 5 in which said step of selectively changing the normal relationship between each chip in a selected column of said memory and corresponding bit storage positions of said word buffers comprises steering the output of each said chip to a selected one of said bit storage positions in said word buffer which is selected in accordance with a previously developed control signal.
Claim 9
Dependent Claim
98 words
A method recited in claim 5 or 6 in which the step of selectively changing said normal relationship between each chip in a selected column of said memory and corresponding bit storage positions of said word buffers includes the step of selectively activating a first group of n' cells, where n' is an integral submultiple of n, to establish a data transfer relationship with said buffer memory instead of activating a second grbup of n' cells in a similar data transferring relationship whereby one chip containing a defect is swapped for an associated chip containing no such defect.
References Cited (Backward Citations)
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